Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Patent
1996-11-27
1998-07-14
Gossage, Glenn
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
711105, 711171, 711172, 395307, 395308, 395886, 371 401, G06F 1200, G06F 1204, G06F 1300, G06F 1340
Patent
active
057819181
ABSTRACT:
A memory system includes a main memory and a memory controller, the main memory including at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of cache FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.
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Lieberman Donald A.
Nemec John J.
Cypress Semiconductor Corp.
Gossage Glenn
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