Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2000-12-13
2004-08-31
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S506000, C345S558000
Reexamination Certificate
active
06784889
ABSTRACT:
TECHNICAL FIELD
The present invention is related generally to the field of computer graphics, and more particularly, to a graphics processing system and method for use in a computer graphics processing system.
BACKGROUND OF THE INVENTION
Graphics processing systems often include embedded memory to increase the throughput of processed graphics data. Generally, embedded memory is memory that is integrated with the other circuitry of the graphics processing system to form a single device. Including embedded memory in a graphics processing system allows data to be provided to processing circuits, such as the graphics processor, the pixel engine, and the like, with low access times. The proximity of the embedded memory to the graphics processor and its dedicated purpose of storing data related to the processing of graphics information enable data to be moved throughout the graphics processing system quickly. Thus, the processing elements of the graphics processing system may retrieve, process, and provide graphics data quickly and efficiently, increasing the processing throughput.
Processing operations that are often performed on graphics data in a graphics processing system include the steps of reading the data that will be processed from the embedded memory, modifying the retrieved data during processing, and writing the modified data back to the embedded memory. This type of operation is typically referred to as a read-modify-write (RMW) operation. The processing of the retrieved graphics data is often done in a pipeline processing fashion, where the processed output values of the processing pipeline are rewritten to the locations in memory from which the pre-processed data provided to the pipeline was originally retrieved. Examples of RMW operations include blending multiple color values to produce graphics images that are composites of the color values and Z-buffer rendering, a method of rendering only the visible surfaces of three-dimensional graphics images.
In conventional graphics processing systems including embedded memory, the memory is typically a single-ported memory. That is, the embedded memory either has only one data port that is multiplexed between read and write operations, or the embedded memory has separate read and write data ports, but the separate ports cannot be operated simultaneously. Consequently, when performing RMW operations, such as described above, the throughput of processed data is diminished because the single ported embedded memory of the conventional graphics processing system is incapable of both reading graphics data that is to be processed and writing back the modified data simultaneously. In order for the RMW operations to be performed, a write operation is performed following each read operation. Thus, the flow of data, either being read from or written to the embedded memory, is constantly being interrupted. As a result, full utilization of the read and write bandwidth of the graphics processing system is not possible.
One approach to resolving this issue is to design the embedded memory included in a graphics processing system to have dual ports. That is, the embedded memory has both read and write ports that may be operated simultaneously. Having such a design allows for data that has been processed to be written back to the dual ported embedded memory while data to be processed is read. However, providing the circuitry necessary to implement a dual ported embedded memory significantly increases the complexity of the embedded memory and requires additional circuitry to support dual ported operation. As space on an graphics processing system integrated into a single device is at a premium, including the additional circuitry necessary to implement a multi-port embedded memory, such as the one previously described, may not be an reasonable alternative.
Therefore, there is a need for a method and embedded memory system that can utilize the read and write bandwidth of a graphics processing system more efficiently during a read-modify-write processing operation.
SUMMARY OF THE INVENTION
The present invention is directed to a system and method for processing graphics data in a graphics processing system which improves utilization of read and write bandwidth of the graphics processing system. The graphics processing system includes an embedded memory array that has at least three separate banks of memory that stores the graphics data in pages of memory. Each of the memory banks of the embedded memory has separate read and write ports that are inoperable concurrently. The graphics processing system further includes a memory controller coupled to the read and write ports of each bank of memory that is adapted to write post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline is coupled to the memory controller to process the graphics data read from the second bank of memory and provide the post-processed graphics data to the memory controller to be written to the first bank of memory. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory. A third bank of memory may be precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.
REFERENCES:
patent: 5353402 (1994-10-01), Lau
patent: 5809228 (1998-09-01), Langendorf et al.
patent: 5831673 (1998-11-01), Przyborski et al.
patent: 5860112 (1999-01-01), Langendorf et al.
patent: 5924117 (1999-07-01), Luick
patent: 5987628 (1999-11-01), Von Bokern et al.
patent: 6002412 (1999-12-01), Schinnerer
patent: 6112265 (2000-08-01), Harriman et al.
patent: 6115837 (2000-09-01), Nguyen et al.
patent: 6150679 (2000-11-01), Reynolds
patent: 6151658 (2000-11-01), Magro
patent: 6272651 (2001-08-01), Chin et al.
patent: 6366984 (2002-04-01), Carmean et al.
patent: 6401168 (2002-06-01), Williams et al.
patent: 6470433 (2002-10-01), Prouty et al.
patent: 6523110 (2003-02-01), Bright et al.
patent: 6587112 (2003-07-01), Goeltzenleuchter et al.
Dorsey & Whitney LLP
Tung Kee M.
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