Memory system and data channel initialization method for...

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules

Reexamination Certificate

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Details

C711S105000, C711S154000, C711S167000, C711S170000, C365S233100

Reexamination Certificate

active

11071586

ABSTRACT:
Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

REFERENCES:
patent: 6137734 (2000-10-01), Schoner et al.
patent: 6272070 (2001-08-01), Keeth et al.
patent: 6442644 (2002-08-01), Gustavson et al.
patent: 6445643 (2002-09-01), Keeth et al.
patent: 6553472 (2003-04-01), Yang et al.
patent: 2003/0026162 (2003-02-01), Matsui

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