Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1992-06-12
1993-10-05
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Bad bit
365193, 36523008, 391 101, 391 102, G11C 1300
Patent
active
052511740
ABSTRACT:
A memory system capable of incorporating defective memory chips is provided. The system includes a first memory chip having a first data signal line and being logically divided into an upper half and a lower half, a controlling circuit responsive to a first indicative address signal and an address strobe signal for outputting therefrom a second indicative address signal and a first and a second output enabling signals, and a second memory chip being logically divided into an upper and a lower halves and having a second data signal line electrically connected to the first data signal line so that only one of the first and second chips is accessible at any time.
REFERENCES:
patent: 3913072 (1975-10-01), Caft
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4128900 (1978-12-01), Lappington
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 5058064 (1991-10-01), Hahm et al.
Acer Incorporated
Kaslow Kenneth M.
LaRoche Eugene R.
Yoo Do Hyun
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