Memory system

Details Memory system Memory system

2007-09-25

2007-09-25

Torres, Joseph D. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S773000

Reexamination Certificate

active

11104735

ABSTRACT:
A system having memory modules for storing nibbles of a word. The nibbles include an error correction/detection code. A memory controller is response to clock pulses to produce a read command. A synchronizer is responsive to the read nibbles and an associated read strobe signal for synchronizing the read nibbles and the read strobes to the clock pulses. A detection section is responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each of the read strobes is expected. The detection system is responsive to each one of the read strobes and the produced time window for producing, for each one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals. Each one of the NIBBLE ERROR signals indicates whether the corresponding one of the read strobes is within the produced window or is absent from such window.

REFERENCES:
patent: 4030067 (1977-06-01), Howell et al.
patent: 4564944 (1986-01-01), Arnold et al.
patent: 6574746 (2003-06-01), Wong et al.
patent: 7051265 (2006-05-01), Tsao et al.
patent: 7065697 (2006-06-01), Briggs et al.
patent: 2003/0070133 (2003-04-01), Bauman et al.

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