Memory system

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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Details

C365S230010, C365S239000, C365S189011, 37, 37, C711S118000

Reexamination Certificate

active

06285607

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory system. In particular, the present invention relates to a memory system having a plurality of memory devices for storing and retrieving data structures, where the system is arranged and configured so that each data structure is divided into portions which are respectively stored in different memory devices.
DESCRIPTION OF THE RELEVANT PRIOR ART
Such memory systems, for example high performance solid state file storage devices, are already known and are used for storage and retrieval of data structures which are wider than the width of an individual addressable memory location in each individual memory device in the system. For example, a memory system may have 16 memory devices, each memory device storing 4 bits at each addressable memory location, so that data structures which are 64 bits wide may be stored (each 4 bit portion being stored in a different memory device). Thus, each data structure is stored in memory space spanning a plurality of memory devices with different portions of the data structure stored at the same address but in different devices. To store or retrieve a data structure, the address is applied simultaneously to each memory device in the memory system.
It is a disadvantage of this type of memory system that if one or more of the memory devices contains a defective memory location, then the only addresses which may be validly used for the entire memory system are the addresses which correspond to locations which are non-defective in all of the memory devices in the system. If each device has several different defective locations then this causes a dramatic reduction in memory capacity because a defective location in one device renders that location unusable in all of the devices. Thus, the percentage of usable locations in the memory system may be much lower than the percentage of usable memory locations in the device having most defective locations.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a new and improved memory system that obviates or mitigates the foregoing disadvantage.
It will be understood that the term “memory location” refers herein to the smallest number of bits or bytes which are independently addressed in each memory device; however, it will also be appreciated that the smallest number of bits that are addressed may be a multiple of the smallest number of bits that can be addressed. The term “cell” refers herein to a large plurality of memory locations, typically a cell may store, for example, 512 bytes or 8192 bytes. The term “width” when applied to a memory device herein refers to the number of bits or bytes in a memory location.
According to a first aspect of the present invention there is provided a memory system comprising:
a plurality of memory devices, where at least one of the memory devices has a defective memory location;
defect mapping means associated with each memory device having a defective location, for recording a representation of the location of the or each defective memory location;
a controller for accessing the defect mapping means and for writing data structures to and reading data structures from the memory devices; and
host interface means for conveying a host address and associated data structures between a host and the controller;
the system being arranged and configured so that data structures are divided into portions which are respectively stored in different memory devices, and, in use, the controller accesses the defect mapping means and thereby generates on a per device basis an address corresponding to a non-defective memory location within that device, whereby different addresses may be applied to different devices. By virtue of the present invention, a memory system typically having a high usable percentage of memory locations is obtained because each memory device is treated independently, which has the effect that defective memory locations only reduce the memory capacity of the device in which they are located.
According to a second aspect of the present invention there is provided a controller for use with a memory system having a plurality of memory devices, at least one of the devices having a defective memory location, and the system having defect mapping means associated with each memory device having a defective location, where the system is arranged and configured so that each data structure is divided into portions which are respectively stored in different memory devices, the controller being arranged for accessing the defect mapping means and thereby generating on a per device basis an address corresponding to a non-defective memory location within that device, whereby different addresses may be applied to different devices.
Preferably, the controller is arranged to organise the memory locations in each memory device into groups of memory locations (where each group is herein called a cell) so that if any cell contains a defective memory location then the entire cell is considered to be defective. This has the advantage that the defect granularity (cell size) of the memory system may be selected for optimum performance. Preferably, the controller has a host address converter for converting the host address to an intermediate address, a translator for accessing the defect mapping means and constructing a memory address for a non-defective memory location for each device using the intermediate address and where necessary the defect mapping means, and a data transfer unit for applying the memory addresses to the respective devices.
Preferably, the translator also determines the number of data structures which may be transferred in an uninterrupted sequence. Conveniently, an indication of this number may be stored in a register or set of registers.
Preferably, the defect mapping means is in the form of a non-volatile memory such as a PROM (programmable read-only memory); conveniently the defect mapping means for each device having a defective location is located on a single a FLASH EPROM. Alternatively, but less preferred, the defect mapping means may be located on another type of storage medium such as a magnetic disk, a CD-ROM, or such like.
Preferably, the defect mapping means has an entry for each cell in each of the memory devices.
Preferably, the memory devices are DRAM devices.
Alternatively, the memory devices may be any convenient type of memory, such as SRAM, EEPROM or FLASH EPROM devices. According to a third aspect of the present invention there is provided a method of storing and retrieving data structures, where the data structures are divided into portions which are respectively stored in different memory devices; the method comprising the steps of:
providing a plurality of memory devices, where at least one of the memory devices has a defective memory location;
providing defect mapping means associated with each memory device having a defective location;
on a per device basis, determining with reference to any defect mapping means associated with that device an address of a non-defective memory location within that device;
applying the respective determined addresses to the devices; and
either reading a data structure from or writing a data structure to the respective memory locations accessed by the respective determined addresses.
It will be appreciated that the determined addresses may be concatenated to form a single address having a plurality of fields.


REFERENCES:
patent: 5321697 (1994-06-01), Fromm et al.
patent: 5544312 (1996-08-01), Hasbun et al.
patent: 5644539 (1997-07-01), Yamagami et al.

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