Memory supporting multiple address protocols

Details Memory supporting multiple address protocols Memory supporting multiple address protocols

1998-05-12

2000-09-12

Palys, Joseph E.

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

Loading initialization program

712 15, 711170, G06F 9445

Patent

active

061192260

ABSTRACT:
The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined as rows of the memory array designated for storage of data. The decoders decode a memory access requested for the data. The memory access request may be in either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array, a decoder, a control, and a logic gate. The decoders decode a memory access request to select a row of memory array. The control has an output for outputting either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical "Exclusive Or" of the control signal and a corresponding bit of the memory access request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.

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