Memory subsystem voltage control and method

Details Memory subsystem voltage control and method Memory subsystem voltage control and method

2006-10-24

2006-10-24

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C713S001000, C713S002000, C713S100000, C711S105000, C711S170000, C365S185110, C365S226000

Reexamination Certificate

active

07127622

ABSTRACT:
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a nonvolatile memory configured to store a preferred memory device voltage configuration corresponding to a preferred operating voltage of the memory device. The preferred memory device voltage configuration is readable by a host and the circuit is responsive to a command to modify the voltage to the memory device in accordance with the preferred memory device configuration. The voltage to the memory device is modified for improved performance and compatibility of the memory device with a host system.

REFERENCES:
patent: 4545010 (1985-10-01), Salas et al.
patent: 4654787 (1987-03-01), Finnell et al.
patent: 5097437 (1992-03-01), Larson
patent: 5237674 (1993-08-01), Mohme et al.
patent: 5253357 (1993-10-01), Allen et al.
patent: 5375084 (1994-12-01), Begun et al.
patent: 5418924 (1995-05-01), Dresser
patent: 5430859 (1995-07-01), Norman et al.
patent: 5509138 (1996-04-01), Cash et al.
patent: 5621685 (1997-04-01), Cernea et al.
patent: 5684973 (1997-11-01), Sullivan et al.
patent: 5727182 (1998-03-01), Fukushima et al.
patent: 5727208 (1998-03-01), Brown
patent: 5757712 (1998-05-01), Nagel et al.
patent: 5953243 (1999-09-01), Capps, Jr. et al.
patent: 5960462 (1999-09-01), Solomon et al.
patent: 6067593 (2000-05-01), Schade
patent: 6092146 (2000-07-01), Dell et al.
patent: 6170059 (2001-01-01), Pruett et al.
patent: 6185629 (2001-02-01), Simpson et al.
patent: 6226729 (2001-05-01), Stevens et al.
patent: 6256217 (2001-07-01), Rondeau et al.
patent: 6298426 (2001-10-01), Ajanovic
patent: 6317812 (2001-11-01), Lofgren et al.
patent: 6351827 (2002-02-01), Co et al.
patent: 6362996 (2002-03-01), Chang
patent: 6363450 (2002-03-01), Lash et al.
patent: 6434034 (2002-08-01), Wallace et al.
patent: 6473831 (2002-10-01), Schade
patent: 6510099 (2003-01-01), Wilcox et al.
patent: 6516381 (2003-02-01), Hamilton et al.
patent: 6769069 (2004-07-01), Nguyen
patent: 6845444 (2005-01-01), Su et al.
patent: 6904506 (2005-06-01), Wu et al.
patent: 2002/0145919 (2002-10-01), Lamb et al.
patent: 2002/0184579 (2002-12-01), Alvarez, II et al.
patent: 2004/0039745 (2004-02-01), Evans et al.
patent: 2004/0089717 (2004-05-01), Harari et al.
patent: 2004/0158771 (2004-08-01), Garnett et al.
patent: 2004/0243753 (2004-12-01), Horowitz et al.

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