Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1997-11-13
2002-05-28
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S154000, C711S105000, C713S400000, C713S401000, C365S193000, C365S194000
Reexamination Certificate
active
06397312
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory subsystem configured of a memory operated in synchronism with a clock or a memory module including a plurality of memories functioning as a large-capacity memory, or more in particular to a memory subsystem capable of high-speed data transfer using a simple mechanism.
2. Description of the Related Art
A large-scale semiconductor device system such as a computer using semiconductor devices is so configured that the parts of the system operate in synchronism with a clock, and signals such as data signals and address signals are input and output in synchronism with a clock. For example, a clock is supplied to each semiconductor device from a clock source through a wiring of equal length. The semiconductor device on the output side outputs a signal in synchronism with an edge of the clock and the semiconductor device at the receiving end receives a signal in synchronism with, an edge of a shift clock shifted by a predetermined amount of phase, or the semiconductor on output side outputs a signal in synchronism with an edge of a shift clock shifted by a predetermined amount of phase and the semiconductor at the receiving end receives a signal at a timing synchronized with an edge of the clock. In either case, however, the signal received by the semiconductor device at the receiving end develops a skew corresponding to the propagation time. As long as the clock frequency is low, the deterioration of the shift clock accuracy due to signal variations or the skew caused by the propagation time pose substantially no problem. With a high clock frequency, however, such phenomena pose a great problem.
Several system configurations for high-speed operation have been suggested for solving these problems. A first scheme, which is called a bidirectional strobe scheme, uses a strobe signal in the transmission in the two directions apart from a clock. A signal line for propagating the data signal to be transmitted and a strobe signal line are installed in parallel. Therefore, substantially no skew is generated and the same phase relation is maintained. In the bidirectional strobe scheme, a strobe signal suitable for retrieval is output in the same direction as the data signal in whichever direction the data signal is transmitted, and therefore the transmission signal can always be retrieved at an optimum timing. Nevertheless, a shift clock generating circuit for generating a shift clock is required of the semiconductor devices at the two ends. In addition, a strobe signal line is required with an input circuit and an output circuit thereof.
A second scheme is called a unidirectional strobe scheme, in which a clock is supplied from a first semiconductor device to a second semiconductor device, and a signal is transmitted from the first semiconductor device to the second semiconductor device in synchronism with the clock, while a signal is transmitted from the second semiconductor device to the first-semiconductor device in synchronism with a strobe signal. In the unidirectional strobe scheme, a transmission signal can be retrieved at an always optimum timing in whichever direction the signal is transmitted.
Both of the above-mentioned conventional schemes make it necessary to generate a shift clock and, in order to generate a signal shifted by an accurately predetermined amount, a DLL (delay locked loop) circuit is used. The DLL circuit, however, is very complicated and large in circuit scale, and requires a large chip area and a large power supply. Provision of this circuit in the semiconductor device, therefore, gives rise to a problem of an increased cost due to a larger chip area and an increased power consumption. Also, the DLL circuit is for producing a desired delay signal by selecting the number of stages of a delay line connected in a multiplicity of stages, and therefore causes a jitter corresponding to one stage of delay. Further, a DLL circuit including a plurality of parallel delay lines arranged with the output of a front line connected to the input of a rear line to produce a desired phase poses the problem that the jitter is magnified by a factor equal to the number of lines arranged. This jitter deteriorates the phase control accuracy and displaces the timing of retrieval, thereby forming a stumbling block to an increased speed.
SUMMARY OF THE INVENTION
The object of the present invention is to realize a memory system capable of high-speed data transmission with a simple configuration.
According to the present invention, in order to achieve the above-mentioned object, there is provided a memory subsystem comprising means for outputting data in synchronism with a clock or a data strobe signal from a controller or a memory and transmitting the clock or the data strobe signal through a clock signal line or a data strobe signal line arranged in parallel with a data signal line, wherein a delay circuit causes a predetermined delay in the clock signal line or the data strobe signal line, so that the clock or the data strobe signal, as the case may be, has a phase suitable for retrieving the data signal and the data signal can be retrieved directly with the received clock or the data strobe signal at the destination. This configuration eliminates the need of the DLL circuit and therefore does not pose the above-mentioned problem. Also, even in the case where data are required to be transmitted and retrieved with reference to both the leading and trailing edges of a clock as when using a DDR-SDRAM, all that is required is to insert a 180° DLL circuit for generating a signal 180° out of phase, and therefore less jitter is generated.
The above-mentioned predetermined delay is the one by which the clock or the data strobe signal comes to have a phase suitable for retrieving the data signal, and represents one half of a minimum transition period of the write data or the read data, or in the case of DDR-SDRAM, a time corresponding to one fourth the clock period.
The delay circuit is realized by a circuit with a long wire to lengthen the signal propagation time through the signal line or by a delay line using a delay element.
The clock signal line is desirably matched in impedance with the data strobe signal line.
The delay circuit is desirably inserted between the controller and the memory. In the event that insertion between the controller and the memory is impossible due to a limited space, the delay circuit can be arranged outside the controller and the memory.
The clock is applied to the clock signal line either from the controller or from the clock source. In the case where the clock is applied from the clock source, the clock to the controller is branched or supplied in parallel. The data strobe signal can be the clock received by the memory. In such a case, the memory changes the read data at the transition edge of the received clock when transmitting the read data, and the data strobe signal line is connected to the clock signal line in the neighborhood of the memory.
Conventionally, a shift clock generating circuit is included in the controller and the memory in order that the clock or the data strobe signal may have a phase suitable for retrieving the transmission data. As a result, the phase cannot be adjusted by lengthening the signal line and a DLL circuit is required. According to the present invention, in contrast, the phase is adjusted outside the chip, and therefore a simple configuration with a lengthened signal line or the like can be used for phase adjustment.
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patent: 5835956 (199
Nakano Masao
Sato Kotoku
Taguchi Masao
Takemae Yoshihiro
Tomita Hiroyoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
McLean Kimberly
Yoo Do Hyun
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