Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-03-07
2003-01-21
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S153000
Reexamination Certificate
active
06509216
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a memory structure embedded with a thin film transistor and a method for fabricating the memory structure.
2. Description of Related Art
As integration of an integrated circuit continuously increases, the area occupied by a device is accordingly reduced. One memory cell of a dynamic random access memory (DRAM) device typically includes a transistor and a capacitor. Therefore, when the integration increases, fabrication cost can be greatly reduced. In addition, since the DRAM has good capabilities for read and write, DRAM device has been one memory device having been widely used.
An embedded DRAM, which is one type of various DRAM devices, has a memory cell array and a logic circuit array formed at the peripheral area to the memory cell array. The memory cell array and the logic circuit array are integrated together into one DEAM chip, resulting in fast data access speed. This allows the DRAM device can be used in a system, which needs a great amount of data access with fast speed, such as an image processing system.
A trend in fabrication technology is toward to larger chip area and narrower line width, so as to have higher integration and have greater capabilities in the same device size. The fabrication can also be reduced. However, the chip area and the line width usually limits the increase of integration. It is difficult to further increase the device integration when the integration has reached to some high degree. How to increase the integration is now an issue in fabrication for developing.
SUMMARY OF THE INVENTION
The invention provides a memory device with a thin film transistor, which can be formed on a substrate without using additional mask.
The invention provides a memory device with a thin film transistor, which is formed on a shallow trench isolation structure, whereby the available chip area can be effective used, and the integration is effectively increased under the same size of the chip area.
As embodied and broadly described herein, the invention provides a method for fabricating a memory device with thin film transistor. The method includes providing a substrate which has shallow trench isolation (STI) structures in the substrate at a memory array region and a logic circuit region, where the memory array region includes a memory cell region and a memory peripheral region that is peripheral to the memory cell region. The memory peripheral region is also separated by the STI structures. A first dielectric layer and a thin film conductive layer are sequentially formed over the substrate. The thin film conductive layer at the logic region is doped. Also and, the threshold voltage adjustment is performed on the thin film conductive layer at the logic region. A second dielectric layer is formed over the substrate at the logic region. The thin film conductive layer at the memory region is doped, so as to reduce resistance of the thin film conductive layer thereon. A conductive layer and a cap layer are sequentially formed over he substrate. The substrate is patterned by photolithography and etching processes, whereby a gate structure at the memory cell region, a gate structure at the memory peripheral region, and a gate structure above the STI structure at the logic circuit region. The portion of the thin film conductive layer covered by the second dielectric layer still remains. A source/drain region is formed in the substrate at each side of the gate structure at the memory cell region. Then, a source/drain region is formed in the the memory peripheral region of the substrate at each side of the gate structure, and simultaneously a source/drain region is formed in the thin film conductive layer at each side of the gate structure above STI structure at the logic circuit region. The layers, including the first dielectric layer and the thin film conductive layer, over the substrate at the logic circuit region are patterned by photolithography and etching processes to form a gate structure at the logic circuit region. A source/drain region is formed in the substrate at each side of the gate structure at the logic circuit region. A metal salicide layer is formed on the gate structure and the source/drain region at the logic circuit region. A capacitor is formed at the memory region with contact on the source/drain region with respect to the each gate structure.
The invention also provides a structure of a memory device with thin film transistor. The structure of the memory device includes a substrate. The substrate has shallow trench isolation structures, a thin film transistor, a memory cell transistor, a memory peripheral transistor, and logic circuit transistor. The shallow trench isolation structures are located in the memory cell region, the logic circuit region, and also on the memory peripheral region to isolate the memory peripheral region from the memory cell region and the logic circuit region. The thin film transistor with a thin film substrate is located above at least one of the shallow trench isolation structures.
In the foregoing of the invention, the feature is that a thin film transistor is additionally formed above the shallow trench isolation structure at the logic circuit region. The available substrate area can be more efficiently utilized, and therefore the more transistors can be formed with the same substrate area. The device integration is then effectively increased.
Moreover, the formation of the thin film transistor is compatible with the current fabrication process for the embedded DRAM. There is no need of an extra step with additional photomask in the invention.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5470776 (1995-11-01), Ryou
patent: 5898189 (1999-04-01), Gardner et al.
patent: 6204099 (2001-03-01), Kusumoto et al.
patent: 6294424 (2001-09-01), Kang et al.
patent: 05183133 (1993-07-01), None
patent: 05183134 (1993-07-01), None
Chien Sun-Chieh
Kuo Chien-Li
Estrada Michelle
Fourson George
J.C. Patents
United Microelectronics Corp.
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