Memory structure and method making

Details Memory structure and method making Memory structure and method making

2006-12-12

2006-12-12

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

C438S598000, C257SE27103

Reexamination Certificate

active

07148088

ABSTRACT:
A memory structure has a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections. Each intersection includes an electrically linear resistive element in series with a voltage breakdown element.

REFERENCES:
patent: 5070383 (1991-12-01), Sinar et al.
patent: 5625220 (1997-04-01), Liu et al.
patent: 5714416 (1998-02-01), Eichman et al.
patent: 5818749 (1998-10-01), Harshfield
patent: 5835396 (1998-11-01), Zhang
patent: 5856775 (1999-01-01), Stopper
patent: 5926415 (1999-07-01), Shin
patent: 6002607 (1999-12-01), Dvir
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6185121 (2001-02-01), O'Neill
patent: 6185122 (2001-02-01), Johnson et al.
patent: 2001/0055838 (2001-12-01), Walker et al.
patent: 0 680 087 (1995-11-01), None
patent: WO 96/19837 (1996-06-01), None

Affiliated with

Also associated with

Rating

Memory structure and method making does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory structure and method making, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory structure and method making will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3667555