Memory structure and fabricating method thereof

Details Memory structure and fabricating method thereof Memory structure and fabricating method thereof

2007-12-13

2009-08-18

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S311000, C257SE27092

Reexamination Certificate

active

07576381

ABSTRACT:
A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

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patent: 2007/0287245 (2007-12-01), Hieda et al.
patent: 2008/0188052 (2008-08-01), Winstead et al.

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