Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-06-18
1999-06-15
Beausoliel, Jr., Robert W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39518218, 395468, 395472, 711141, 711144, G06F 1120
Patent
active
059130210
ABSTRACT:
In a memory state recovering apparatus, processors process data and a main memory holds data necessary for the data processing at the processors. Caches are provided to correspond to the processors and have the function of issuing an invalidation transaction to specify the invalidation of the data to maintain the consistency of the data. A before image buffer combines an address in the main memory with the data held in the location indicated by the address and stores the combination. A memory access control section stores in the buffer memory the address targeted in the main memory and the data stored in the location indicated by the address in accordance with the invalidation transaction issued from the caches. With this configuration, the time required for a checkpoint process can be shortened, thereby improving the system performance.
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P. Bernstein, "Sequoia: A Fault-Tolerant Tightly Coupled Multiprocessor for Transaction Processing", IEEE Computer, 21(2):37-45 (1988).
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Beausoliel, Jr. Robert W.
Elisca Pierre E.
Kabushiki Kaisha Toshiba
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