Memory standard cell macro for semiconductor device

Details Memory standard cell macro for semiconductor device Memory standard cell macro for semiconductor device

1995-12-21

1997-12-16

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257204, 257369, 257390, 257909, 365230, H01L 27108

Patent

active

056988761

ABSTRACT:
A semiconductor device of a memory-macro type can be designed within a short time to have a desired storage capacity, which does not occupy a large area, so as to reduce the chip cost. The semiconductor device includes a memory macro having sub-memory macros, each sub-memory macro having a DRAM memory-cell array, and a row decoder and a column decoder for selecting any desired memory-cell from the memory cell of the array. The memory macro also includes a control-section macro having a DC potential generating circuit for generating various DC potentials required to drive the sub-memory macros. At least one of the sub-memory macros is combined with the control-section macro to form the memory macro as a one-chip memory capable of storing an integral multiple of N bits.

REFERENCES:
patent: 4295149 (1981-10-01), Balyoz

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