Memory space compression technique for a sequentially accessible

Details Memory space compression technique for a sequentially accessible Memory space compression technique for a sequentially accessible

1997-05-20

2000-12-26

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Address formation

Varying address bit-length or size

710 52, 341 76, G06F 700

Patent

active

061674990

ABSTRACT:
A technique for conserving digital memory space is disclosed. This technique includes sequentially transmitting a first address and a second address on a first bus coupled to a FIFO memory. The first address is stored in the memory and compared to the second address to determine a first value corresponding to a difference between the first and second addresses. This first value is written in the memory to represent the second address and has a bit size smaller than the second address. A method to decode the first value to regenerate the second address is also disclosed. These techniques may be further enhanced by only storing an address in a sequential access memory when it differs from the most recently stored address in the memory.

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