Memory sense scan circuit and test interface

Details Memory sense scan circuit and test interface Memory sense scan circuit and test interface

2011-01-11

2011-01-11

Kerveros, James C (Department: 2117)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S203000

Reexamination Certificate

active

07869293

ABSTRACT:
A scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command includes a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implement scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.

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