Memory semiconductor device with reduced sense amplifier area

Details Memory semiconductor device with reduced sense amplifier area Memory semiconductor device with reduced sense amplifier area

2002-01-10

2004-09-14

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S905000

Reexamination Certificate

active

06791132

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and particularly to a technique which is applicable effectively to the sense amplifier section of DRAM (Dynamic Random Access Memory).
DRAM (Dynamic Random Access Memory) has an area for forming memory cells and a peripheral circuit area for forming circuits, e.g., sense amplifiers, for writing data onto the memory cells and reading data out of memory cells. A memory cell is made up of a capacitor C and a data transfer MISFET Qs which is connected at one end to the capacitor C, and it is formed at the intersection of a word line WL which is the gate electrode of the MISFET Qs and a bit line (data line) BL which is connected with one of source/drain regions of the MISFET Qs.
A sense amplifier SA is a circuit connected between bit lines BL and adapted to amplify a voltage difference of the bit lines BL.
In the trend of microstructuring of memory cells, the spacing between bit lines has become smaller, giving rise to the need of a breakthrough scheme for the connection of the bit lines to the sense amplifiers SA and the layout of the sense amplifiers SA.
For example, Japanese Patent Unexamined Publication No. Hei 10(1998)-303387 describes a technique of reducing the area for forming sense amplifier circuits based on the connection of a sense amplifier (SA
0
) to a main bit line pair (MBL
0
, /MBL
0
) by use of a sub bit line pair (SBL
0
, /SBL
0
) which extend along word lines.
Another Japanese Patent Unexamined Publication No. Hei 7(1995)-254650 (which corresponds to U.S. Pat. Nos. 5,602,772 and 5,629,887) describes a technique of relaxing the line interval in word line direction at the layout design of a sense amplifier block based on the arrangement of sense amplifier blocks in multiple columns along the word lines, whereas as conventionally sense amplifier blocks can be arranged in only one column in one cell array, by increasing the number of diffusion layers and wiring layers for connecting gate electrodes of transistors within the sense amplifier block.
SUMMARY OF THE INVENTION
In accompanying the reduction of bit line interval, the inventors of the present invention have studied the following technical affairs.
In the case of forming memory cells at all intersections of word lines and bit lines as shown in
FIG. 1
, the memory cell area can be reduced and the bit line interval can also be reduced. For example, for a memory cell structure shown in FIG.
33
and
FIG. 34
, which will be explained in detail later, a memory cell can be formed in an area of 6F
2
(where F denotes the minimum working dimension).
A sense amplifier circuit, which is connected between bit lines as mentioned above, is also connected with common lines (common source lines) for driving the sense amplifier SA to the high or low level. The peripheral circuit area has the formation of recharge circuits and Y-switch circuits, and these circuits are connected with a precharge voltage feed line and input/output lines.
In order to reserve between bit lines an area (line b
1
) for the contact with these lines, five lines (b) are formed in spacings (a) of four bit lines (refer to FIG.
32
).
However, in the case of forming a memory cell in the area occupied by one MISFET (refer to FIG.
3
and FIG.
4
), i.e., when a memory cell has an area of 4F
2
, the bit line spacing becomes F, and the application of the above-mentioned technique is limited as will be explained in detail in the following.
In the case of forming bit lines of the memory cell forming area by using a Levenson's line-and-space mask, the bit lines are formed in different phases alternately. In forming five lines in the spacings of four bit lines as mentioned above, the five lines need to be formed in different phases alternately, and there will arise restrictions on the line layout.
It is an object of the present invention to provide a layout scheme for the sense amplifier forming area capable of dealing with the microstructured bit lines of memory cells.
Another object of the present invention is to provide a scheme of reducing the sense amplifier forming area.
These and other objects and novel features of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
Among the affairs of the present invention disclosed in this specification, representatives are briefed as follows.
In the inventive semiconductor integrated circuit device, first data lines which are formed on a first layer and first lines which are formed on a second layer different from the first layer are connected in a first connecting area between a first memory array area and a sense amplifier area, and second data lines which are formed on the first layer and second lines which are formed on the second layer are connected in a second connecting area between a second memory array area and the sense amplifier area. This layout scheme can reduce the line interval of the first and second lines which are connected to the first and second data lines, respectively.
By forming data transfer lines (IO), precharge lines (VBLR), and power and ground lines (CSN, CSP) on the first layer, these lines can have a relatively large line interval, and consequently it becomes possible to have a connecting section for the connection between the first and second lines formed on the second layer and MISFETs, etc. (elements) formed below the firs, layer.
By forming the data transfer lines (IO) on the second layer, these lines can have a larger thickness and the delay of signals caused by the line resistance can be alleviated. Particularly, by placing a switch area, in which the data transfer lines (IO), etc. are connected, between the first and second memory cell areas and the sense amplifier area, the line layout over the switch area is relaxed and the data transfer lines can be formed here.
Owing to the formation of the first and second lines on the other layer than that of the first and second data lines, the first and second lines can be formed irrespective of the phase relation at the formation of the first and second data lines, and consequently it becomes possible to reduce the line interval of the first and second lines.


REFERENCES:
patent: 5325336 (1994-06-01), Tomishima et al.
patent: 5602772 (1997-02-01), Nakano et al.
patent: 5629887 (1997-05-01), Nakano et al.
patent: 6046924 (2000-04-01), Isobe et al.
patent: 7-254650 (1995-10-01), None
patent: 10-303387 (1998-11-01), None

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