Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent
1999-05-04
2000-07-04
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
36523006, G11C 700
Patent
active
060848049
ABSTRACT:
An integrated circuit memory array has a plurality of rows of memory cells, each row of memory cells being coupled to a respective row line for enabling the memory cells of the row. A row driver of the memory array provides a row voltage on the row line. A pull-up transistor of the row driver pulls up the row voltage in response to a row control signal. A parasitic diode of the pull-up transistor is coupled at its anode to the row line and is adapted to pull the row voltage down from a high state voltage to a diode drop voltage plus a low state voltage in response an enable block signal coupled to the cathode of the parasitic diode. A pull-down transistor of the row driver also pulls down the row voltage in response to the row control signal.
REFERENCES:
patent: 5477489 (1995-12-01), Wiedmann
patent: 5572461 (1996-11-01), Gonzalez
patent: 5835402 (1998-11-01), Rao et al.
patent: 5949712 (1999-09-01), Rao et al.
Lucent Technologies - Inc.
Nguyen Viet Q.
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