Memory row/column replacement in an integrated circuit

Details Memory row/column replacement in an integrated circuit Memory row/column replacement in an integrated circuit

2007-04-03

2007-04-03

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C714S710000, C714S711000, C714S042000, C714S723000

Reexamination Certificate

active

10889159

ABSTRACT:
An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array (50) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry (92). A selected one of these vectors stored in the actual solution storage circuitry (92) is then used to determine rows and columns in memory array (20) to be replaced with redundant rows (22, 24) and redundant columns (26).

REFERENCES:
patent: 6421286 (2002-07-01), Ohtani et al.
patent: 2004/0163015 (2004-08-01), Nadeau-Dostie et al.
Shoukourian et al., “An Approach for Evaluation of Redundancy Analysis Algorithms,” vol. 0-7695-1242-9/01, IEEE 2001, pp. 51-54.
Kawagoe et al., A Built-In Self Repair Analyzer (CRESTA) for Embedded DRAM, Proc. IEEE Int. Test Conference, ITC 2000, pp. 567-574.

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