Memory row architecture having memory row redundancy repair...

Details Memory row architecture having memory row redundancy repair... Memory row architecture having memory row redundancy repair...

2007-07-27

2010-02-16

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

07663949

ABSTRACT:
The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the plurality of redundancy memory sections is equal to the number of the plurality of normal memory sections, and a redundancy memory section is implemented in one side of each of the plurality of normal memory sections. In addition, the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an odd serial number make up a first memory row redundancy repair module, and the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an even serial number make up a second memory row redundancy repair module.

REFERENCES:
patent: 7295479 (2007-11-01), Yoon et al.
patent: 7304900 (2007-12-01), Shibata et al.
patent: 7570526 (2009-08-01), Han

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