Memory row and column redundancy

Details Memory row and column redundancy Memory row and column redundancy

2008-01-18

2010-06-15

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030, C365S201000, C365S225700

Reexamination Certificate

active

07738308

ABSTRACT:
In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.

REFERENCES:
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patent: 2003/0103394 (2003-06-01), Koshikawa
patent: 2006/0052247 (2006-03-01), Beaudegnies
PCT Search Report for PCT/US06/32222, publication date May 21, 2007, 7 pages attached.

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