Memory request reordering in a data processing system

Details Memory request reordering in a data processing system Memory request reordering in a data processing system

2005-12-13

2005-12-13

Sparks, Donald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S158000, C711S167000, C711S168000, C710S039000, C710S040000

Reexamination Certificate

active

06976135

ABSTRACT:
Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.

REFERENCES:
patent: 4590586 (1986-05-01), Zenk et al.
patent: 5581729 (1996-12-01), Nishtala et al.
patent: 5642494 (1997-06-01), Wang et al.
patent: 6026461 (2000-02-01), Baxter et al.
patent: 6240458 (2001-05-01), Gilbertson

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