Memory request interlock

Details Memory request interlock Memory request interlock

2000-08-14

2004-10-26

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S156000

Reexamination Certificate

active

06810470

ABSTRACT:

BACKGROUND
This invention generally relates to computer systems. In particular, the invention relates to memory controllers in computer systems.
Memory controllers are used to control the flow of data between clients of a computer system, such as a central processing unit (CPU) and graphics controller, and the memory, such as dynamic RAM (DRAM). These controllers typically buffer read and write requests from the clients to the memory.
A typical controller is illustrated in
FIG. 1. A
client
22
desires for various reads and writes to be performed to a memory
32
. The write requests are sent to a write buffer
26
and the read requests are sent to a read buffer
24
. To assure that the read and write buffers
24
,
26
can handle the requests, handshaking is performed between the buffers
24
,
26
and the client
22
. An arbiter
28
selects read and write requests from the corresponding buffer
24
,
26
to be performed in a selected order. The buffers
24
,
26
handshake with the arbiter
28
to determine when requests should be sent to the arbiter
28
.
After the arbiter
28
selects the requests, the selected requests are sent to the sequencer
30
for execution. The sequencer
30
processes the requests in the received order and generates all the timing information for accessing the memory
32
.
Typically, the arbiter
28
does not take the read and write requests in the order that they were received by the buffers
24
,
26
. The arbiter
28
may select the requests which most efficiently use the memory
32
. For instance, the arbiter
28
may select a group of read requests prior to a single write request. This situation may occur when all the read requests were associated with a page currently active in the memory device. Performing all of these read requests first avoids a page miss penalty. Another situation where out of order execution occurs is when the read buffer
24
has significantly more pending requests than the write buffer
26
, or vice versa.
Performing read and write requests out of order to the same memory address is usually undesirable. In many systems, different processes or even the same process performing sequential tasks, can share data only by writing to and reading from the system or video memory. In this situation, reads and writes to the same location need to be executed in the order received by the buffers
24
,
26
. A basic memory controller device, as shown in
FIG. 1
, cannot assure a proper execution order. As a result, incorrect read data is returned to the client
22
.
Accordingly, it is desirable to provide a memory controller which eliminates these erroneous data transfers.
SUMMARY
A memory controller for use in a computer system. The controller has a buffer having an input configured to receive read and write requests. Each request has an associated memory address. For a selected received request, prior received requests out of a set of the received requests are determined. For each determined prior received request, that request's memory address is compared to the selected request's memory address to see if they match. If a match exists, the selected request is prevented from being memory executed.


REFERENCES:
patent: 5418973 (1995-05-01), Ellis et al.
patent: 5432918 (1995-07-01), Stamm
patent: 5778413 (1998-07-01), Stevens et al.
patent: 5895492 (1999-04-01), Greenspan et al.
patent: 6009426 (1999-12-01), Jouenne et al.
patent: 6145052 (2000-11-01), Howe et al.
patent: 6279050 (2001-08-01), Chilton et al.

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