Memory repair system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment

Reexamination Certificate

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Details

C714S723000, C365S200000, C365S201000

Reexamination Certificate

active

07949908

ABSTRACT:
A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element including the non-operational memory cells. A first repair sub-circuit soft repairs the memory by substituting the selected memory elements with the redundant memory elements. A second repair sub-circuit hard repairs the memory based on the substitutions.

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Kawagoe, Tomoya et al; “A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs”; ITC International Test Conference; Jan. 2000; pp. 567-574.
Ohler, Philipp et al; “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy”; Proceedings 12thIEEE European Test Symposium, Freiburg, Germany, May 2007; 6 pages.
Ohler, Philipp et al; “Analyzing Test and Repair Times for 2D Integrated Memory Built-In Test and Repair”; Proceedings 10thIEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Krakow, Poland, Apr. 2007; 6 pages.
Shoukourian, Samvel et al; “SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure”; IEEE Design & Test of Computers; May-Jun. 2004; cover page and pp. 200-207.

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