Memory repair analysis method and circuit

Details Memory repair analysis method and circuit Memory repair analysis method and circuit

2007-03-06

2007-03-06

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S710000

Reexamination Certificate

active

10774512

ABSTRACT:
A method and circuit for repairing a memory array having one or more memory segments each having one spare column and a predetermined number of spare rows common to all segments, the method comprises, while testing the memory array for failures, generating an equal number of unique segment repair solutions for each segment with each segment repair solution including one defective column address, if any, and a number of defective row addresses, if any, corresponding to the predetermined number of spare rows; and, after completing testing, analyzing all segment repair solution combinations consisting of one segment repair solution selected from each segment; and identifying the best segment repair solution combination of combinations having a number of different defective row addresses which is less than or equal to the predetermined number of spare rows.

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Schober, et al., “Memory Built-In Self-Repair”, 2001 Proceedings of the International Trade Conference, Oct. 30-Nov. 1, 2001, p. 995.
Kwon et al., “Linear Search Algorithm for Repair Analysis with 4 Spare Row/4 Spare Column”, Proceedings of the 2nd IEEE Asia-Pacific Conference on ASIC, Cheju Island, Korea, Aug. 28, 2000, paper 15.1.

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