Memory refresh system and operating method thereof

Details Memory refresh system and operating method thereof Memory refresh system and operating method thereof

2011-08-30

2011-08-30

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S207000, C365S196000, C365S189090, C365S189070, C365S194000

Reexamination Certificate

active

08009498

ABSTRACT:
A memory refresh system includes a comparative detection circuit, a logic circuit, and a timing circuit. The comparative detection circuit detects a voltage of the storage capacitor of a memory cell of the memory and generates a corresponding digital code by comparing the voltage with a reference voltage. Each memory cell has a corresponding digital code. The combination of the digital codes of the memory cells forms a first state. After a specific period of time, the voltages of the storage capacitors of the memory cells are once detected by the comparative detection circuit, and corresponding digital codes are generated and combined to form a second state. The logic circuit compares the first state and the second state to determining whether or not to change the refresh period of a refresh period detecting process. The timing circuit changes the refresh period according to the determination result of the logic circuit.

REFERENCES:
patent: 2005/0162931 (2005-07-01), Portmann et al.

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