Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-08-26
2004-04-13
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233500, C365S236000
Reexamination Certificate
active
06721224
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to memories, and more particularly to memory refresh operations.
Dynamic random access memory cells (DRAM cells) need to be refreshed from time to time to restore leaking charge. In older DRAMs, a refresh was initiated by the user (i.e. a system using the memory) by supplying appropriate control signals on the memory input terminals. Some more recent DRAMs hide the refresh from the user. Hidden refresh is desirable for example in pseudo static random access memories, also called pseudo SRAMs or PSRAMs. PSRAMs provide an SRAM-like interface to a DRAM based memory. SRAMs are faster than DRAMs, and SRAMs do not need a refresh, but they are more expensive (due to a larger size of an SRAM cell) and they consume more power. PSRAMs make it easier for a system manufacturer to replace an SRAM with a DRAM based memory.
In order to hide a refresh from the user, the memory access cycles can be extended so that each cycle can accommodate a refresh in addition to a memory access operation. This is inefficient however because the refresh operations can typically be performed less frequently than the memory access operations. In some systems, the refresh operations are hundreds of times less frequent than the memory access operations.
SUMMARY
This section summarizes some features of the invention. Other features are described in subsequent sections. The invention is defined by the appended claims.
In some embodiments of the present invention, the user has an option of extending only selected memory access cycles to accommodate a refresh. This option can be provided as follows. When a refresh becomes pending, the memory will only initiate the refresh at the end of a memory access operation. If there is no memory access operation in progress, the refresh will be postponed. Also, if the user issues a command to perform a memory access operation, but then issues a new command at the end of the memory access operation, the refresh will be postponed to allow the memory to execute the new command. The memory will not initiate the refresh until a time when no new command is pending at the end of a memory access operation.
In some embodiments, the user does not have to issue a new command to suppress a refresh at the end of the current command execution. The user can provide command signals identifying the new command without meeting the setup or any other minimum hold time requirements needed for the command to be issued. For example, in a PSRAM emulating an asynchronous SRAM, the user can suppress the refresh at the end of a current read operation simply by toggling an address input. The user can keep toggling the address input without meeting the setup requirements until the user issues a new command. Thus, the user has to provide an indication of a new command, wherein the indication can be defined as providing the command signals with or without meeting the setup or any other timing requirements.
The invention is not limited to memories with setup requirements. Also, an indication of a new command may involve meeting some of the setup requirements but not meeting other setup requirements.
The memory can be operated as follows. For each command, the user can choose whether the corresponding memory access cycle will be “long” or “short”. A “long” cycle is sufficiently long to accommodate both a memory access operation and a refresh. A short cycle can only accommodate the memory access operation. A new command indication (e.g. a read command indication) is provided by the user at the end of the short cycle memory access operation to block a refresh if one is pending.
The user must periodically perform long cycles to allow a refresh to take place.
If the user makes each cycle either long or short, and periodically performs long cycles to allow a refresh, then the memory access operations are never delayed by a refresh in progress. Therefore, the short cycle timing is predictable. The long cycles can be performed only infrequently as needed to allow a refresh. Further, the refresh can be hidden since the user does not have to know when a refresh is pending and in which of the long cycles the refresh is performed.
In some embodiments, the refresh is performed only at the end of a read operation. The refresh is not performed at the end of write operations. The user is required to periodically perform long read cycles to allow a refresh.
In some embodiments, a refresh can also be performed when the memory is disabled. When the memory becomes enabled, the user is required to either delay memory access or perform a long cycle to accommodate a possible refresh that could have been started when the memory was disabled. If the long cycle is a read, the read data may be delayed since the read operation may be delayed by the refresh.
The above features are exemplary and not limiting. For example, in some embodiments, to suppress a refresh, a new command indication does not have to be issued at the end of the current operation but can be issued before the end of the current operation. Also, the memory may be pipelined to allow a refresh to be initiated before the end of the current operation. The memory may have additional features, e.g. externally initiated refresh capability (non-hidden refresh). The invention is defined by the appended claims.
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Eaton Steve S.
Li Li-Chun
Murray Michael
Lam David
MacPherson Kwok & Chen & Heid LLP
Mosel Vitelic Inc.
Shenker Michael
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