Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1997-10-24
2001-05-01
Nguyen, Than (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S101000, C711S104000, C711S105000, C711S152000, C711S163000, C711S167000
Reexamination Certificate
active
06226709
ABSTRACT:
BACKGROUND OF THE INVENTION
Memory subsystems are typically built with dynamic random access memory (DRAM) devices which retain data by storing electrical charges in capacitive storage cells. Writing to an address charges or discharges the cells depending on the data. Reading from an address depletes the charges, but on-chip circuitry automatically rewrites the data, restoring the cells to their pre-read values. In addition, the cells tend to discharge over time, which unchecked would lead to loss of data.
To prevent this loss of data due to discharge, DRAMs must be periodically refreshed by reading data at some location and writing it back. DRAMs generally provide an atomic refresh operation for this purpose which must be periodically performed on each row. In older DRAMs, this was done by providing a row address and asserting a refresh command. Newer DRAM devices provide an auto-refresh operation, generating a refresh address internally, requiring only that a refresh command be applied externally. During a refresh cycle, all of the DRAM is unavailable.
Similarly, after a read or write, while the charges in a cell are being restored, a DRAM is not accessible. If a multiple device memory system is configured such that adjacent addresses are on the same device, sequential accesses to those adjacent addresses must be delayed while the device is recharging. To increase bandwidth, memory units using DRAMS are interleaved, meaning that memory units are configured so that adjacent memory addresses are not in the same unit. Accessing a series of adjacent addresses will therefore not require a delay because the unit that was previously accessed and is currently recharging is not the unit accessed next.
CPU/memory systems, whether single or multiprocessor, have traditionally relied on a single common data bus connecting all CPUs, memories and other directly addressed ports and peripherals. In these conventional systems, there are in general two ways to implement a memory refresh scheme. One is to have hardware associated with individual memory modules trigger the refresh operations. When a CPU attempts to access an address on a DRAM which is in a refresh cycle, a “stall” signal must stall the system until the refresh is complete. This locks up the bus on average for one half of a refresh cycle.
The other refresh scheme is to have a bus controller schedule refreshes. This method locks up the bus for the duration of the refresh cycle.
In the traditional single data path system, only one memory unit can be accessed by only one CPU at any time. The other CPUs must wait their turn. As an alternative, a cross-bar switch can simultaneously provide multiple data paths between memory modules and CPUs and other ports. Thus all CPUs may access different memory modules simultaneously. An arbiter configures the cross-bar switch according to the needs of the CPUs, and commands the memory modules by sending transaction codes, such as read, write and refresh, to the modules via a transaction bus.
In this cross-bar switch system, where a plurality of CPUs may access a plurality of memory units at the same time, it is crucial that as few memory units as possible be unavailable due to access latency. A highly interleaved system provides a high number of interleaved units, most of which are available at any given time due to the higher number of memory units than CPUs. This greatly increases the probability that addressed memory units will be available.
All of these interleaved memory units need to be refreshed periodically. As with the traditional single data path system described above, each memory module can trigger its own refreshes, or a bus controller, in this case the arbiter, can trigger the refreshes.
In the preferred embodiment, a directory module keeps track of the current “owner” of a cache block as well as who has a copy of the cache block. The “owner” is the CPU or I/O device that has the most up-to-date copy, i.e., the last to modify the block in cache. If no modified copies exist, then the main memory is the owner. When a CPU requests a copy of a cache block, the directory directs the request to the owner of that cache block. The directory therefore maintains data coherency. The directory module does this by maintaining a “line” for every cache block. These lines are associated with the memory units in the system memory and are themselves made up of memory devices requiring periodic refresh.
SUMMARY OF THE INVENTION
The invention resides in refreshing memory units in a computer system. In a highly interleaved system, there are many interleaved units, each needing to be refreshed. If all were to be refreshed simultaneously, an arbiter would first have to wait for all units to be idle. In addition, because memory is unavailable during refresh, there can be no memory accesses during the refresh cycle. It is therefore desirable to refresh only one interleaved unit at a time, so that at most only one unit is unavailable at any given time. However, if the arbiter needed to send a refresh transaction for every unit, it would increase traffic dramatically on the transaction bus, significantly reducing data transfer bandwidth.
In accordance with the invention, a memory system comprises a plurality of memory units and an arbiter which controls access to the memory units and restricts access to a memory unit being refreshed. Refresh registers are associated with the memory units and the arbiter. The refresh registers sequence through memory unit identifiers. Each memory unit is triggered to a refresh when a refresh register associated with the memory unit holds a designated value. The refresh register associated with the arbiter identifies the memory unit being refreshed, allowing the arbiter to restrict access to that memory unit. As a result, the memory units may be refreshed sequentially without ongoing control by the arbiter, which could stall the transaction bus, yet the arbiter retains identification of the unit being refreshed for appropriate control of access to the memory units.
In the preferred embodiment, the memory units are interleaved to the level of memory ranks which are interleaved among memory arrays. The memory arrays are in turn interleaved within memory modules. Each memory module has one refresh register which is associated with all of the memory ranks supported by the module. The refresh registers are counters which increment at intervals of a pre-programmed number of clock cycles. When the refresh register associated with a memory module matches a unique ID, or physical rank number (PRN), associated with a memory rank supported by the memory module, that memory rank is triggered to an auto-refresh cycle. The refresh registers begin counting when the arbiter broadcasts a refresh signal to the memory modules.
It is neither efficient nor necessary for the refreshing to always begin with the same memory rank. If it were the case, that same rank would never be available for access at the beginning of a counting sequence. In other words, if the sequence always had to begin with the same memory rank, the arbiter would not be able to connect a CPU requesting access to that rank until that rank's refresh cycle was over, causing unnecessary delay. For this reason, the arbiter provides a refresh address along with the refresh signal. The memory modules latch this address into their respective refresh registers and begin counting from the address provided.
In an alternative embodiment, rather than having the arbiter broadcast a refresh signal, respective timers are associated with the memory modules and arbiter. The timers are initialized and synchronized as part of a memory configuration, and start the refresh sequence periodically.
The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by
Doren Stephen Van
Goodwin Paul M.
Compaq Computer Corporation
Hamilton Brook Smith & Reynolds P.C.
Nguyen Than
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