Memory refresh control system

Details Memory refresh control system Memory refresh control system

1980-03-28

1981-10-06

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, G11C 700

Patent

active

042939313

ABSTRACT:
In a memory refresh control system for refresh control of a memory having, as refresh addresses, addresses respectively corresponding to combinations of n+N bits, there are provided a refresh control circuit which yields, as refresh addresses, addresses respectively corresponding to combinations of n bits and generates, in a certain period of time, refresh clocks respectively corresponding to the abovesaid addresses for specifying 2.sup.n refresh times, a circuit which divides each of the refresh clock into 2.sup.N in terms of time and an overhead bit generator which is supplied with the divided clocks to produce successively addresses respectively corresponding to combinations of N bits for each divided clock. The n bits available from the refresh control circuit are added with the N bits generated by the overhead bit generator and then applied as an address of n+N to a memory, which is refreshed by the divided clock. The refresh clock divider is composed of monostable multivibrators of suitable time constants, and the overhead bit generator is formed by a counter.

REFERENCES:
patent: 3684897 (1972-08-01), Anderson et al.
patent: 3902082 (1975-08-01), Proebsting et al.
patent: 4084154 (1978-04-01), Panigrahi

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