Memory refresh apparatus and method

Details Memory refresh apparatus and method Memory refresh apparatus and method

2006-07-31

2011-12-13

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S149000, C365S150000, C365S189011, C365S233100, C711S167000, C711S105000, C713S322000

Reexamination Certificate

active

08077535

ABSTRACT:
A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

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