Memory redundancy techniques

Details Memory redundancy techniques Memory redundancy techniques

1999-09-16

2002-11-19

Beausoleil, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S005110

Reexamination Certificate

active

06484271

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to memory devices, and more particularly, but not exclusively, relates to redundant memory systems.
Redundant memory is sometimes used to improve fault tolerance of data storage subsystems. In the case of embedded memory for Integrated Circuits (ICs), redundancy is frequently used to improve manufacturing yield. For Application Specific Integrated Circuits (ASICs), a Hardware Development Language (HDL) macro typically specifies embedded memory. Both primary and redundant memory circuits are often integrally defined by such macros. Consequently, embedded memory macros for ASICs are generally rather complex. Moreover, modifying either the redundant memory scheme or primary memory scheme of these ISE macros may inadvertently impact the scheme not intended to be changed. As an example, it often proves difficult to adjust the amount of redundant memory relative to the amount of primary memory for this type of macro—sometimes introducing race conditions and other problems associated with modifying a complex digital design.
Thus, there is a demand for advancements in the memory redundancy technology. Such advancements may be applied not only to macro-defined embedded memory of a single IC, but also to multi-chip and multi-component systems.
SUMMARY OF THE INVENTION
One form of the present invention is a unique memory device. Another form includes unique redundant memory systems and methods.
A further form is a unique redundant memory macro for defining ICs. This redundant memory macro may be utilized in conjunction with primary memory macros to define an embedded memory with a selectable degree of redundancy.
In another form, a Built-In Self Test (BIST) is implemented with a redundant memory to accommodate yield failures of an associated primary memory. The BIST, redundant memory, and primary memory may be embedded on a common, integrated circuit chip or defined by two or more separate components or integrated circuits.
Still another form includes one or more primary memories associated with a redundant memory. The redundant memory includes a content addressable memory coupled to a replacement memory. Also included is a unique arrangement for providing replacement memory contents in lieu of corresponding primary memory contents that have been determined to be defective.
Further forms, embodiments, aspects, features, and objects of the present invention will become apparent from the description and drawings contained herein.


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