Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-03-15
2004-04-20
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S203000, C365S210130
Reexamination Certificate
active
06724673
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a device for reading a memory and more specifically a read-only memory (ROM, PROM, EPROM, EEPROM).
BACKGROUND OF THE INVENTION
FIG. 1
schematically and partially shows a ROM
2
including a plurality of memory points arranged in rows or word lines and in columns or bit lines. Each memory point includes or not an active cell
4
. The cells
4
are formed of transistors or any other switching circuit likely to connect to a low voltage, currently the ground, the column including this cell. The addressing of cells
4
is performed by rows or word lines WL
6
connected to a line decoder
8
. When an active cell is addressed, it modifies the voltage of the column
10
to which it is connected. In the case of a simple ROM, some cells are made inactive by construction, generally by suppressing of one of their connections, and the corresponding memory point never connects the corresponding column to ground, whatever the corresponding row voltage. Each column
10
is connected to a high supply voltage Vdd via a precharge transistor
12
and is connected to a first input
16
of a sense amplifier
18
. Groups of columns may be associated by multiplexers (not shown). A second input
20
of each sense amplifier
18
is connected to a reference voltage Vref.
To read a memory point, column
10
is brought to a precharge voltage Vpch which is substantially equal to supply voltage Vdd and a high signal is applied on one of rows WL. If the memory point is not programmed, column
10
substantially keeps the precharge voltage on its terminal
16
. However, if the memory point is programmed, column
10
is discharged by a current I which flows through cell
4
. The voltage on line
10
drops and sense amplifier
18
switches when the voltage on terminal
16
falls under reference voltage Vref on terminal
20
. The switching time of amplifier
18
or read time is provided by the following relation:
T=C.&Dgr;V/I
in which &Dgr;V is potential difference Vpch-Vref between inputs
16
and
20
of sense amplifier
18
, beyond which the switching of sense amplifier
18
occurs, C represents the capacitance of column
10
and I represents the value of the current flowing through cell
4
.
The respective values of capacitance C and of current I can be considered as constant. Thus, to reduce read time T, voltage &Dgr;V must be reduced, that is, a voltage Vref as close as possible to Vpch must be chosen. Now, it is necessary to provide a security margin to take technological drifts, voltage offsets at the inputs of amplifier
18
, fluctuations of voltages Vdd and Vref, of low voltage Vss, and of the difference between Vdd and Vpch, into account.
A known solution to optimize the value of Vref consists of performing a differential reading by adding to memory
2
reference columns and by sampling a reference voltage on these reference columns. In practice, a relatively large number of reference columns must be provided, for example, one for eight real columns. This solution thus has the disadvantage of increasing the memory size and cost. Further, each reference column
21
introduces a stray capacitance.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method and a device for reading a ROM, overcoming the above disadvantages.
This object is achieved by means of a device for reading a cell of a memory, including a differential sense amplifier having a first input terminal connected to a cell column and a circuit intended to provide to a second input terminal of the amplifier a reference voltage. The above-mentioned circuit includes a means for storing the voltage of said column and a means for applying as a reference voltage the stored voltage modified by a predetermined amount.
According to an embodiment of the present invention, the presence of a cell translates as a reduction in the voltage of a column and the reference voltage is reduced by a predetermined amount with respect to the stored voltage.
According to an embodiment of the present invention, the above-mentioned circuit includes a first capacitive element intended to store the precharge voltage and a second capacitive element connectable in parallel on the first one to set the value of the reference voltage.
According to an embodiment of the present invention, the capacitive elements are formed of the gate-source, gate-substrate, and gate-drain capacitances of MOS transistors.
The present invention also aims at a method for reading a cell of a memory, including the steps of storing the voltage of a column just before reading; and modifying the stored voltage by a predetermined amount and using the modified voltage as a reference voltage.
According to an embodiment of the present invention, this reading method further consists of comparing the reference voltage with a column voltage.
According to an embodiment of the present invention, this reading method further consists of applying the precharge voltage on a first capacitor; disconnecting the first capacitor from the precharge voltage; and connecting in parallel on the first capacitor a second capacitor.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
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patent: 4669065 (1987-05-01), Ohsawa
patent: 5627790 (1997-05-01), Golla et al.
patent: 5652728 (1997-07-01), Hosotani et al.
patent: 5729492 (1998-03-01), Campardo
patent: 5933366 (1999-08-01), Yoshikawa
patent: 6018481 (2000-01-01), Shiratake
patent: 6370060 (2002-04-01), Takata et al.
patent: 6404666 (2002-06-01), Uchida
patent: 6535434 (2003-03-01), Maayan et al.
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patent: 199 28 598 (1999-12-01), None
Compagne Eric
Covarel Hervé
Dolphin Integration
Duane Morris LLP
Phan Trong
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