Memory read/write arbitration method

Details Memory read/write arbitration method Memory read/write arbitration method

2002-09-09

2003-12-23

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C711S147000

Reexamination Certificate

active

06667926

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory read/write arbitration method, and more particularly relates to a memory read/write arbitration method utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access.
BACKGROUND OF THE INVENTION
Please referring to
FIG. 1
,
FIG. 1
is a diagram showing a conventional structure of personal computer system. As shown in
FIG. 1
, there are a process unit
10
, a host bridge module
12
connected with a memory module
14
and a display device
16
(such as an AGP device) through a memory bus
18
and an AGP bus
20
respectively, and a south bridge module
22
connected with the host bridge module
12
through a PCI bus
24
. The process unit
10
accesses the memory module
14
through a host bus
26
, the host bridge module
12
and the memory bus
18
, and there are PCI devices
28
accessing the memory module
14
through the PCI bus
24
, the host bridge module
12
and the memory bus
18
.
Inside the host bridge module
12
, there is a memory controller
30
embedded, wherein the embedded memory controller
30
, which is used to interface the process unit
10
and the memory bus
18
, comprises: an IOQ, at least one read request FIFO queue (Rfifo queue), at least one write request FIFO queue (Wfifo queue), and at least one memory arbitrator.
Please referring to
FIG. 2
,
FIG. 2
is a diagram showing a conventional arbitration structure of memory controller according to FIG.
1
. As shown in
FIG. 2
, the Rfifo queue
50
comprises N+1 read entries
54
(N+1 command read requests) and the Wfifo queue
52
comprises M+1 write entries
56
(M+1 command write requests), wherein N and M are integers equal to or greater than zero. A plurality of comparators
58
are used for comparing the associated address of each read entry
54
of the Rfifo queue
50
to that of each write entry
56
of the Wfifo queue
52
.
For example, when the front read entry
54
of the Rfifo queue
50
is scheduled to be forwarded to a memory arbitrator
60
, the associated address of the front read entry
62
is compared to that of each valid write entry
56
. If there is a match in the i write entry of the Wfifo queue
52
, this front read entry
62
will be suspended until all the write entries prior to the i write entry and also the i write entry have forwarded to the memory arbitrator
60
. If the associated address of each write entry
56
does not match that of the front read entry
62
, this front read entry
62
will be forwarded to the memory arbitrator
60
. In the computer architecture, this operation for reducing the read latency is known as the read around write operation. On the other hand, the front read entry
62
in the Rfifo queue
50
will not be forwarded to the memory arbitrator
60
when a match comes.
Under the read around write operation, the Wfifo queue
52
gets priority over the Rfifo queue
50
when the Rfifo queue
50
is empty or an associated data fifo (not shown) of the Rfifo queue
50
is full, wherein the associated data fifo is used to save the temporary responses of read requests.
Please also refer to FIG.
1
. Since the process unit
10
is eager to get data from memory module
14
for process, designers always concern about how to speed up the read cycle, the retrieval of the data from the memory module
14
and how to reduce the read latency, so that the read around write operation is widely utilized to let the Rfifo queue
50
frequently has priority over the Wfifo queue
52
. However, as long as the write cycles are issued from the process unit
10
and completed in the host bus
26
, it is not so much concerned that when or how fast the write cycles are forwarded and completed in the memory bus
18
. Thus, the utilization of memory bus
18
is decreased apparently, and the row hit rate is polluted and decreased by breaking consecutive same type entries, since the row hit probability among either consecutive same type read entries or consecutive same type write entries is considerably high under the read around write operation.
SUMMARY OF THE INVENTION
In view of the background of the invention described above, since how to speed up the read cycle, the retrieval of the data from the memory module and how to reduce the read latency are concentrated principally, the conventional memory read/write arbitration method just serves the higher priority for the Rfifo queue than for the Wfifo queue in read around write operation. Therefore, the row hit is polluted and decreased by breaking consecutive same type entries, and moreover, the utilization of memory bus is decreased, and the frequency of accessing delay during the transitions from read to write and from write to read is increased obviously.
It is the principal object of the present invention to provide a memory read/write arbitration method. In the present invention, the memory read/write arbitration method performs a judgment on the Rfifo queue and the Wfifo queue. Two judgment steps are applied in the memory read/write arbitration method. A first sub-judgment step is used to evaluate whether the command write request of Wfifo queue can be forwarded to a second sub-judgment step or not by preset adaptive conditions, such as whether the number of command write requests is equal to or greater than the high threshold to the number of command write requests, and whether the pending number of command read requests is less than the low threshold to the pending number of command read requests, etc. The second sub-judgment step is used to evaluate if the command write request from the first sub-judgment step has the priority over the command read request of Rfifo queue, or if the command read request of Rfifo queue has the priority over the command write request from the first sub-judgment step under preset adaptive conditions, such as if the number of continuous command write requests is under the low threshold to the number of continuous command write requests, or between the high threshold to the number of continuous command write requests and the low threshold to the number of continuous command write requests, and meanwhile, the page address accessed by current command write request is equal to the page address opened by accesses of a plurality of command write requests and command read requests previously.
In accordance with the aforementioned purpose of the present invention, the present invention provides a memory read/write arbitration method for increasing the row hit rate and the bandwidth utilization of memory bus. The memory read/write arbitration method comprises: providing a arbitrator; providing a read request fifo queue having a plurality of command read requests; providing a write request fifo queue having a plurality of command write requests; performing a judgment step to determine if a command write request of the plurality of command write requests has priority over a command read request of the plurality of command read requests to be forwarded, or if the command read request of the plurality of command read requests has priority over the command write request of the plurality of command write requests to be forwarded, wherein the judgment step comprises: performing a first sub-judgment step to obtain a signal Cmd_Wrt_Req_Mask, and the command read request has priority over the command write request to be forwarded when the signal Cmd_Wrt_Req_Mask is enabled, and otherwise, the command write request is forwarded to be performed in a second sub-judgment step when the signal Cmd_Wrt_Req_Mask is disabled under at least one of a plurality of first-step conditions, such as that the number of command write requests is equal to or greater than the high threshold to the number of command write requests, that the pending number of command read requests is less than the low threshold to the pending number of command read requests, and etc; and performing the second sub-judgment step with the command write requests from the first sub-judgment step and the command read requests to obt

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