Memory read strobe pulse optimization training system

Details Memory read strobe pulse optimization training system Memory read strobe pulse optimization training system

2006-09-12

2006-09-12

Bragdon, Reginald G. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S168000, C711S169000, C713S400000, C713S401000, C713S500000, C713S503000, C365S193000, C365S194000

Reexamination Certificate

active

07107424

ABSTRACT:
A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.

REFERENCES:
patent: 6646929 (2003-11-01), Moss et al.
patent: 6658523 (2003-12-01), Janzen et al.
patent: 6735709 (2004-05-01), Lee et al.
patent: 6889334 (2005-05-01), Magro et al.
patent: 6941433 (2005-09-01), Libby et al.
patent: 7016240 (2006-03-01), Avakian et al.

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