Memory read control circuit

Details Memory read control circuit Memory read control circuit

2008-07-23

2010-11-02

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S191000, C365S193000, C365S194000, C365S233100

Reexamination Certificate

active

07826281

ABSTRACT:
A DQS detection circuit13detects a preamble of a DQS signal outputted from RAM11. An up/down counter14counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, counts down a number of trailing edges of the DQS signal after the preamble corresponding to a data read request, and detects that a counted value is set to 0. A flip-flop circuit FF2makes a mask signal MS) a low level when the counted value is set to 0. An AND circuit AND2makes the DQS signal maskable with a mask signal MS.

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patent: 2005-276396 (2005-10-01), None
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