Memory rank decoder for a multi-rank Dual Inline Memory...

Details Memory rank decoder for a multi-rank Dual Inline Memory... Memory rank decoder for a multi-rank Dual Inline Memory...

2007-09-04

2007-09-04

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S105000, C365S230080

Reexamination Certificate

active

11010182

ABSTRACT:
The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).

REFERENCES:
patent: 5332922 (1994-07-01), Oguchi et al.
patent: 6502161 (2002-12-01), Perego et al.
patent: 6683372 (2004-01-01), Wong et al.
patent: 7200021 (2007-04-01), Raghuram
patent: 2002/0112119 (2002-08-01), Halbert et al.
Natarajan et al., “A Study of Performance Impact of Memory Controller Features in Multi-Processor Server Environment”, ACM International Conference Proceedings Series, vol. 68, Proceedings of the 3rd Workshop on Memory Performance Issues: in Conjuction with the 31st International Symposium on Computer Architecture, pp. 80-87, ACM Press, Jun. 2004.

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