Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2008-03-27
2011-10-25
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S152000, C711SE12001
Reexamination Certificate
active
08046559
ABSTRACT:
A method, device, and system are disclosed. In one embodiment the method includes grouping multiple memory requests into multiple of memory rank queues. Each rank queue contains the memory requests that target addresses within the corresponding memory rank. The method also schedules a minimum burst number of memory requests within one of the memory rank queues to be serviced when the burst number has been reached in the one of the plurality of memory rank queues. Finally, if a memory request exceeds an aging threshold, then that memory request will be serviced.
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International Search Report and Written Opinion mailed Nov. 3, 2009 for International Patent Application No. PCT/US2009/038522; 10 pages.
David Howard
Gorbatov Eugene
Hanebutte Ulf R.
Zheng Hongzhong
Bataille Pierre-Michel
Intel Corporation
Reynolds Derek J.
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