Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-10-13
2009-02-17
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S212000
Reexamination Certificate
active
07493456
ABSTRACT:
A memory controller includes an address queue with address queue locations that may expand to store address commands that point to consecutive locations in memory. In this manner, multiple address commands may combine together in a common expanded address queue location. In one embodiment, each address queue location includes a main information portion and a supplemental information portion. The supplemental information portion is smaller than the main information portion. The main information portion stores the target address information of a first address command. When the address queue receives an address command with a target address that is consecutive to the target address of the first command, then the supplemental address portion stores a subset of the target address of the second command.
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Brittain Mark Andrew
Maule Warren Edward
Retter Eric Eugene
Handelsman Libby
International Business Machines - Corporation
Kahler Mark P
Verbrugge Kevin
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