Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2002-06-24
2004-10-26
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S151000, C711S158000
Reexamination Certificate
active
06810471
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This present invention relates to a memory protection technology, and it particularly relates to a method and a circuit for individually specifying attributes on access by address ranges.
2. Description of the Related Art
Microprocessors and other data processing apparatuses execute access for read, write and so forth by issuing addresses to a memory or other devices (hereinafter referred to simply as a “device”) in the logical address space. Depending on the addresses, logical regions may often be defined where read and write are both permitted, where only read may be permitted, or where neither read nor write is permitted. These characteristics concerning access (hereinafter referred to as “access attributes” or simply as “attributes”) may sometimes be set in units of logical regions called “pages,” for instance. To prohibit or restrict the rewrite or read of data of a device by setting attributes is generally called protection.
One example of a memory protection circuit in which attributes are individually specified by address ranges can be found in U.S. Pat. No. 6,021,476. In this circuit according to the U.S. patent, each of address ranges for a plurality of logical regions can be specified, and priority is fixedly predetermined for each of the logical regions. And when an address issued by a microprocessor is contained in an address range for a plurality of logical regions, the logical region with the highest priority (hereinafter referred to as “the highest priority region” also) is selected, and access is executed in accordance with the attributes determined for the logical region.
For example, where 4 KB of operating system (hereinafter described as “OS”) program region and 12 KB of user program region are mapped into a 16 KB RAM, a region of 16 KB is, in general, first divided into four regions of 4 KB each, and then one of them is assigned to the “OS program region” and the remaining three to the “user program region.” This requires at least four times of setting operations. In the case of the above-mentioned U.S. patent, however, the purpose is attained if the whole region of 16 KB is mapped into the “user program region” and then the 4 KB portion of it only is mapped to overlap in the “OS program region” and the priority for this 4 KB is set higher. This requires the defining of two regions only, thus making the setting simpler.
However, the inventor has come to realize that because of fixed priorities given to the logical regions in the above-mentioned patent, there is room for improvement in the setting change following the change of memory map. For instance, consider a case where the attributes for a 30 KB logical region containing addresses 0xffff8000 (0xffff8000 indicates ffff8000 in the hexadecimal notation; hereinafter, “0x” represents hexadecimal in the similar manner) to 0xfffff7ff are full access, which means both readable and writable, and cacheable, and the attributes for a 2 KB logical region containing addresses 0xfffff800 to 0xffffffff are read only and cacheable. In the case of the above-mentioned U.S. patent, when the priorities are fixed in advance as
logical region
0
<logical region
1
<logical region
2
, that is, when logical region
2
is fixed as the highest priority region, the setting is made as:
For Logical Region
0
:
The address range is 32 KB from 0xffff8000 to 0xffffffff.
The attributes are full access and cacheable.
For Logical Region
1
:
The address range is 2 KB from 0xfffff800 to 0xffffffff.
The attributes are read only and cacheable.
Here, consider a case of a change of memory map in which the attributes for 6 KB only of the 30 KB full-access and cacheable logical region are changed to read-only and uncacheable. Then the setting will be made as:
For Logical Region
0
:
The address range is 32 KB from 0xffff8000 to 0xffffffff.
The attributes are full access and cacheable.
For Logical Region
1
:
The address range is 8 KB from 0xffffe000 to 0xffffffff.
The attributes are read only and uncacheable.
For Logical Region
2
:
The address range is 2 KB from 0xfffff800 to 0xffffffff.
The attributes are read only and cacheable.
Here, the 2 KB logical region, which was read only and cacheable before the change of memory map, retains the same address range and the same attributes of read only and cacheable even after the change of memory map, but, for that logical region, the address range and attributes set for logical region
1
before the memory map change must be changed to the setting for logical region
2
. Thus, where a memory protection circuit is set by the program of a microprocessor, the changing of the program is complex and therefore requires an extremely careful work.
Moreover, where memory is protected by dynamically changing the attributes by a program, it is naturally desired that there be fewer processing steps for the setting change.
SUMMARY OF THE INVENTION
The present invention has been made in view of foregoing problems, and an object thereof is to make simpler the modification of the program necessary to change the setting of a memory protection circuit or to reduce the number of processing steps required for the setting change.
A preferred embodiment according to the present invention relates to a memory protection circuit which controls access, in a logical address space, to a device from a data processing apparatus such as a microprocessor. This circuit comprises: an address range register unit which respectively specifies address ranges of a plurality of logical regions in the logical address space; an attribute register unit which specifies an access attribute for each of the logical regions; an address comparison unit which judges whether or not an access request address for the device is contained in each of the logical regions; a priority register unit which specifies priority of access for each of the logical regions; an attribute determining unit, when there is a logical region or more which is judged as containing the access request address, which specifies and outputs an attribute specified for a logical region whose priority is highest among the logical regions; and a register setting unit which is capable of repeatedly setting the address range register unit, the attribute register unit and the priority register unit.
Representative of the “device” is a memory as mentioned earlier. Yet it is not necessary for the device to be memory as long as it is accessible via logical address space similar to memory map. For example, the device may be a memory-mapped I/O device. Moreover, optional devices, the appearance of which is indistinguishable between memory and I/O device, such as various extended bus cards, are “devices” as long as at least part of them is mapped into a logical address space.
Similarly, the “memory protection circuit” does not necessarily have memory as its target of protection, but is a general term for circuits that protect arbitrary devices mapped to the logical address space in the same way as the memory mapped thereto.
Since this circuit can set the priorities of the logical regions variably and repeatedly, the setting change of address range and attributes necessitated by the setting change of protection becomes simple.
This circuit may further include a protection error unit which outputs a protection error signal when none of the logical regions is judged to contain the access request address or when an access attribute for the access request address is not of permitting nature. This structure may be realized by, for example, a gate element which outputs the protection error signal as active when, for example, all of comparison results by the address comparison unit indicate “not contained”.
This circuit may further include a unit which outputs a protection error signal when the access attribute for the access request address indicates “access prohibited”. As an example, the protection error signal is outputted in a case where the attribute of an access request address is “read only” while the data processing apparatus is
Christensen O'Connor Johnson & Kindness PLLC
Sanyo Electric Co,. Ltd.
Thai Tuan V.
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