Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2003-01-02
2004-12-28
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S163000, C711S170000
Reexamination Certificate
active
06836836
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a memory protective administrative apparatus and method for a computer for protecting memory access between programs, and particularly to the realization of process at exception of address conversion at real time, and the reduction in memory amount used for memory protective administration.
BACKGROUND ART
Since the memory protective administrative apparatus carries out process at exception of address conversion at real time, a tree-like hierocratical segment table is used as the procedure for searching a physical address with respect to a virtual address that an exception has occurred. By using the tree-like hierocratical segment table, it is possible to make search time finite length, and to suppress a memory using amount used by the memory protective device. Hereupon, the segment table is a table which holds a pointer to a next hierarchy or a pointer to a page table, and a flag showing that addresses below that hierarchy are null. The page table is a table comprising a virtual address at every size (page size) determined by the system and an entry holding the correspondence to a physical address.
The memory protective technique as described above has the problems as follows:
(1) In the preparation, deletion and memory using amount of the segment table, wasteful cost sometimes occurs. For example, even a memory region of only two pages, its page table sometimes belongs to two segment tables.
(2) As the memory region becomes large, necessary segment tables increase.
Further, in a case where a huge memory region like a frame buffer is protected in a procedure similar to a normal memory region, there poses a problem that the page table becomes huge, and the cost for preparing and deleting page table entries increases.
DISCLOSURE OF THE INVENTION
The present invention has been accomplished in consideration of the aforementioned circumstances. An object of the invention is to reduce the memory amount used for a segment table and a page table, and at the same time, to lower costs when memory regions are prepared or deleted.
It is a further object of the present invention to solve the problem that the size of a memory region of a page table becomes huge, that is, a problem that the size becomes large in proportional to the number of pages, in connection with a physically continuous memory region.
According to one aspect of the present invention, the following constitution is employed in order to solve the aforementioned objects. That is, as will be described in detail later with reference to
FIG. 2
, when a new memory region is prepared, the virtual address administrative apparatus receives size as input to assign a virtual address region above the size. At this time, a top address of a region smaller than size (indicated by S
1
) covered by one (1) entry of a segment tale of the minimum hierarchy assigns a virtual address so as to be necessarily aligned (making a multiple of certain number is called align) to the size S
1
. The virtual address is secured by the size S
1
from the address aligned. During using the region, a portion larger than size actually used in the memory region is also not reused. With respect to regions of size larger than S
1
, hierarchies in which size can be covered by 1-entry are searched to assign the virtual address aligned similarly.
The page table is variable in length and has size of a region, and a page entry for a size part. The page table is linked to an entry corresponding to a top virtual address of a segment table in the hierarchy for align.
By the procedure mentioned above, as will be described later with reference to
FIG. 3
, a page table for a predetermined memory region is received without fail in one page table not depending on size. A region of large size is linked directly to a segment table of an upper hierarchy.
Since a top of an address covered by a segment table entry coincides with a top address of a memory region without fail, when addresses are searched, sizes are compared to discriminate whether or not the page is effective.
Since by the above-described procedure, the page table is prepared independently every memory region, when a memory region is owned jointly by a plurality of protective spaces, if a protective attribute is the same, one page table can be owned jointly. Even in a case where the protective attribute is different, in a case where the protective attribute is administered by a memory region unit, the protective attribute is not held every page but is held by a combination of a protective space and a memory region to enable holding in common.
Further, by the above-described procedure, with respect to a memory region comprising physically continuous pages, only a top physical address and size of a region are held as will be described later with reference to
FIG. 5
, it is not necessary to hold physical addresses for all pages in a page table as in a normal memory region. That is, the top virtual address is obtained from a position of a segment table linked. At exception of address conversion, a difference between an exceptional address and a top physical address are added to a top physical address to thereby obtain a corresponding physical address.
The aforementioned one aspect and other aspects of the present invention are defined in claims, and will be described in detail hereinafter with reference to the drawings.
REFERENCES:
patent: 5282274 (1994-01-01), Liu
patent: 5555387 (1996-09-01), Branstad et al.
patent: 64-17137 (1989-01-01), None
patent: 1-125640 (1989-05-01), None
Anderson Matthew D.
Frommer William S.
Frommer & Lawrence & Haug LLP
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