Memory protection circuit for EPROM

Details Memory protection circuit for EPROM Memory protection circuit for EPROM

1994-09-20

1996-04-09

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

36518504, 365196, G11C 700

Patent

active

055068065

ABSTRACT:
An erasable programmable read-only memory (EPROM) includes a plurality of EPROM cells arranged in a matrix having a plurality of rows and a plurality of columns, and a plurality of digit lines each connected in common to drains of the EPROM cells included in a corresponding one column of EPROM cells. A Y-selector receives a Y-address of a given address for selecting one digit line of the digit lines so as to connect the selected digit line to a sense amplifier. Each of the digit lines is connected to one of reading-inhibition circuits having a reading-inhibition information storing EPROM cell, so that when the reading-inhibition information storing EPROM cell of the reading-inhibition circuits are in a written condition, the digit line is forcibly maintained at a predetermined logic level. The EPROM can inhibit the reading of any bit or bits and any area of an EPROM.

REFERENCES:
patent: 4791612 (1988-12-01), Yoshida
patent: 5337281 (1994-08-01), Kobayashi
patent: 5381369 (1995-01-01), Kikuchi

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