Memory protection arrangement

Details Memory protection arrangement Memory protection arrangement

1987-09-23

1990-06-05

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

36518907, 36523008, 365228, 365195, 371 671, G11C 700, G11C 800

Patent

active

049319930

ABSTRACT:
A memory protection arrangement comprises a controller, a memory, first and second memory address self-hold circuits, first and second address comparators and a memory write signal controlling gate. The controlling gate is responsive to the output signal of the second comparator to control memory write such that a current address falling within a range between memory addresses of the first and second memory address self-hold circuits inhibits the memory from being written. The controller then performs an abnormality processing to stop the operation. The operation is stopped as soon as a write signal develops in a program area in the event that the program is caused by a terminal device to tend to undergo runaway and the program is protected from destruction. Through initialization by turn-on of a power supply, the program can be started to process with the operation.

REFERENCES:
patent: 4402044 (1983-08-01), McDonough et al.
patent: 4521852 (1985-06-01), Guttag
patent: 4521853 (1985-06-01), Guttag
patent: 4724521 (1988-02-01), Carron et al.
patent: 4744062 (1988-05-01), Nakamura et al.
patent: 4796235 (1989-01-01), Sparks et al.

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