Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-07-26
2005-07-26
Namazi, Mehdi (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S100000, C711S154000, C710S049000, C712S005000, C714S003000
Reexamination Certificate
active
06922764
ABSTRACT:
A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.
REFERENCES:
patent: 4533995 (1985-08-01), Christian et al.
patent: 5572682 (1996-11-01), Garibay et al.
patent: WO 01/43134 (2001-06-01), None
Dortu Jean-Marc
Feurle Robert
Schmölz Paul
Täuber Andreas
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Namazi Mehdi
Stemer Werner H.
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