Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Reexamination Certificate
2007-05-01
2007-05-01
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Accelerating charge or discharge
C365S203000, C365S205000
Reexamination Certificate
active
11257816
ABSTRACT:
A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier input and a bitline conditioner precharges and readjusts the selected bitline to a precharge threshold. A sense amplifier produces a data output that is based on the sense amplifier input.
REFERENCES:
patent: 4692902 (1987-09-01), Tanaka et al.
patent: 5138579 (1992-08-01), Tatsumi et al.
patent: 5790458 (1998-08-01), Lee et al.
patent: 5936888 (1999-08-01), Sugawara
patent: 6018487 (2000-01-01), Lee et al.
patent: 6282114 (2001-08-01), Hanriat et al.
patent: 6404677 (2002-06-01), Lee
patent: 6754122 (2004-06-01), Wada et al.
patent: 6914822 (2005-07-01), Briner
patent: 6992915 (2006-01-01), Kang et al.
patent: 2003/0174545 (2003-09-01), Wada et al.
patent: 2006/0023532 (2006-02-01), Hush et al.
Garlick & Harrison & Markison
Mai Son L.
Sigmatel, Inc.
Stuckman Bruce E.
LandOfFree
Memory, processing system and methods for use therewith does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory, processing system and methods for use therewith, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory, processing system and methods for use therewith will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3814165