Memory processing in a microprocessor

Details Memory processing in a microprocessor Memory processing in a microprocessor

2002-04-19

2004-04-13

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

C711S109000, C711S154000, C711S219000

Reexamination Certificate

active

06721867

ABSTRACT:

FIELD
The invention relates to memory processing in a microprocessor.
BACKGROUND
A microprocessor comprises an external and/or internal memory indicated by means of alignment boundaries for storing data. An arithmetic-logic unit (ALU) carrying out calculations in the microprocessor employs registers to temporarily store the data to be processed in the calculations. Data is transferred according to need between the memory and the register. Alignment problems are associated with memory processing. An alignment problem means that it is more difficult to process a memory addressing, which cannot be fitted within the alignment boundaries, in the memory addressing sense than such data that accurately starts from one alignment boundary and ends at another alignment boundary. Processing the data that cannot be fitted into the alignment boundaries can be referred to as unaligned data access. Current microprocessors generally employ either byte addresses (8 bits) or word addresses (16 bits) for addressing the memory, but larger alignment boundaries also exist, such as 32 bits. An alignment boundary determines from which part of the memory data can be read and how data is stored in the memory.
U.S. Pat. No. 6,061,779 discloses a solution in which a separate data alignment buffer is used for unaligned data access. The solution is not very flexible as it employs a multiplexer, to which alternatives for reading data from various parts in the memory are fixedly determined.
In
FIGS. 2A
,
2
B and
2
C commands in a microprocessor instruction set are used to describe prior art methods for processing memory in a microprocessor. The contents of the registers in each cycle are described using comments, which are separated from the actual commands with a semicolon. The contents of the memory employed are described below in more detail in a memory
100
shown in
FIG. 1
, the 64-bit contents at the beginning thereof is indicated as a hexadecimal figure “10 08 08 07 07 05 05 10”. Section “08 08 07 07” is to be retrieved from the memory.
In
FIG. 2A
a general purpose processor that is capable of addressing memory by 32-bit alignment boundaries, carries out a memory search using five processor cycles in such a manner that 32 bits are at first loaded from a memory address ADDRESS indicating the beginning of the 64-bit contents to register R
0
. Then register R
0
is shifted eight bits to the left. After this 32 bits are loaded from a memory address ADDRESS+1, or from the middle of the 64-bit contents, to register R
1
. Next, register R
1
is shifted 24 bits to the right. Finally a logical OR operation is carried out between registers R
0
and R
1
, and the result thereof is placed into register R
0
. The solution thus requires the use of two registers, two memory searches, two register shifts and one logical OR operation.
In
FIG. 2B
the Texas Instruments® TMS320C55x processor is employed that addresses the memory in 16-bit mode. The memory search can generally be carried out using three cycles in such a manner that a 40-bit accumulator AC
0
is at first loaded with the first 16 bits from the 64-bit contents and the contents of the accumulator are shifted 24 bits to the left. Then the following 16 bits from the 64-bit contents are loaded into the accumulator and shifted 8 bits to the left. Finally the accumulator is loaded with the following 16 bits from the 64-bit contents, which are shifted 8 bits to the right. The solution thus requires three memory searches and three shifts.
In
FIG. 2C
the Texas Instruments®TMS320C64x processor that is able to address memory in 8-bit mode can be used to carry out the memory search in a single cycle. Using a particular command LDNW (Load Non-Aligned Word) the second, third, fourth and fifth byte of the 64-bit contents are read into register A
0
. The solution is efficient as regards the use of cycles but it requires an 8-bit memory addressing. The search of unaligned data still remains a problem if said data cannot be fitted into the 8-bit alignment boundary.
BRIEF DESCRIPTION
It is an object of the invention to provide an improved microprocessor. According to an aspect of the present invention there is provided a microprocessor comprising a memory indicated by means of alignment boundaries for storing data, at least one register for storing data used during calculation, memory addressing means for indicating the memory by means of the alignment boundaries and for transferring data between the memory and the register, and a hardware shift register, which can be shifted with the accuracy of one bit, and which comprises a data loading zone and a guard zone, and the memory addressing means transfer data including a memory addressing which cannot be fitted into the alignment boundary between the memory and the register through the data loading zone in the hardware shift register, and the hardware shift register is arranged to process data using shifts and utilizing the guard zone.
The invention is based on the idea that a hardware shift register, which can be shifted with the accuracy of one bit, can be used to solve the problem associated with the search of unaligned data. A hardware shift register comprises both a data loading zone and a guard zone. The solution is adaptable and allows to efficiently process memory.


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Panda et al., “Data and Memory Optimization Techniques for Embedded Systems,” pp 149-206, ACM, Apr. 2001.*
Edwards, White Paper, “Performance Evaluation of the TMS320C64x Architecture and C Compiler,” pp 1-21, Blue Wave Systems, Inc., Oct. 25, 2000.

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