Memory precharge scheme using spare column

Details Memory precharge scheme using spare column Memory precharge scheme using spare column

1995-04-13

1996-07-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518905, 371 102, G11C 700

Patent

active

055329659

ABSTRACT:
Performance is improved for a memory array composed of storage elements which require a preconditioning operation prior to writing new data or rewriting old data. At least one spare column of memory elements is provided. The spare column is preconditioned during a time when it is not used for data storage. During a write operation to a memory address, data are written into the preconditioned spare column instead of the column associated with the memory address. The memory address is reassociated with the spare column, and the column with which it was previously associated becomes a new spare column which is preconditioned during restore and made ready for use during a subsequent memory access. In this way time for the preconditioning operation is hidden, and no delay for preconditioning is incurred. A plurality of spare columns allows each spare column to be preconditioned during a plurality of memory cycles.

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Fitzgerald et al., "Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement", IBM J. of Res. & Dev., vol. 24, No. 3, pp. 291-298, May 1980.

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