Memory power management using prefetch buffers

Details Memory power management using prefetch buffers Memory power management using prefetch buffers

2005-08-30

2005-08-30

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Generating prefetch, look-ahead, jump, or predictive address

Reexamination Certificate

active

06938146

ABSTRACT:
A system and method for improving memory performance and decreasing memory power requirements is described. To accomplish the improvements, a prefetch buffer is added to a memory controller with accompanying prefetch logic. The memory controller first attempts to satisfy memory requests from the prefetch buffer allowing the main memory to stay in a reduced power state until accessing it is required. If the memory controller is unable to satisfy a memory request from the prefetch buffer, the main memory is changed to an active power state and the prefetch logic is invoked. The prefetch logic loads the requested memory, returns the request memory to the requester, and loads memory likely to be requested in the near future into the prefetch buffer. Concurrent with the execution of the prefetch logic, the memory controller returns the requested data. Following the retrieval from main memory, the memory controller may place the main memory into a reduced power state immediately, or after a selected interval, based upon the likelihood of a subsequent memory request miss.

REFERENCES:
patent: 5719800 (1998-02-01), Mittal et al.
patent: 5901103 (1999-05-01), Harris et al.
patent: 6014751 (2000-01-01), Kardach et al.

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