Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-04-17
2002-03-26
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S105000
Reexamination Certificate
active
06363460
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to circuitry and protocols associated with operating a memory device, and more particularly, to methods for controlling paging operations in a memory device.
BACKGROUND OF THE INVENTION
FIG. 1
is a simplified functional diagram of a memory device
200
that represents any of a wide variety of currently available memory devices. The central memory storage unit of the memory device
200
is a memory array
202
which is typically arranged in a plurality of banks, with two such banks
204
A and
204
B shown in the Figure. The memory array
202
includes a plurality of individual memory elements (not shown) for storing data, with the memory elements typically arranged in separately addressable rows and columns. Those skilled in the art oftentimes refer to a collectively addressable subset of the array
202
as a “page.” Typically, a single row of memory elements in a bank of the array constitutes a particular page. In
FIG. 1
, a plurality of pages
206
A and
206
B are depicted, corresponding with banks
204
A and
204
B, respectively.
As known to those skilled in the art, particular locations within the memory array
202
are addressable by Address signals that external circuitry (not shown) provides to the memory device
200
. Also, external circuitry provides a plurality of Control or command signals that are used to designate the particular memory access type and/or sequence of memory accesses. As depicted in
FIG. 1
, a control/address logic circuit
208
receives the Control signals and Address signals, which may be provided in parallel signal paths, serially, or some combination. The control/address logic circuit
208
then applies a plurality of internal control signals to control the timing and sequence of operations accessing the banks
204
A and
204
B via access circuits
210
A and
210
B, respectively. Those skilled in the art will understand that the depicted access circuits
210
A and
210
B represent a collection of various functional circuit components commonly found in memory devices. Examples include row and column address latch, buffer, and decoder circuits, sense amplifiers and I/O gating circuitry, and other well-known circuits adapted for particular memory device implementations. Data written to and read from the memory array
202
is transferred from and to external circuitry via a data I/O circuit
212
and the access circuits
210
A and
210
B.
When access to a particular memory page is complete, and the memory page is then “closed,” a precharge operation is performed to prepare the memory device for a subsequent memory access. The precharge operation requires a certain amount of time for its completion, and therefore limits the speed with which a sequence of memory operations can be performed. By organizing the memory array
202
to have multiple banks
204
A and
204
B with associated multiple access circuits
210
A and
210
B, the precharge time can, in some instances, be “hidden.” For example, if a first memory access is to bank
204
A, and a subsequent memory access is to bank
204
B, precharge operations associated with bank
204
A can occur while initiating memory access operations to bank
204
B. However, successive memory access operations to a single bank still result in precharge time intervals during which memory access operations cannot be performed.
Some attempts have been made to minimize those data transfer interruptions caused by precharge time intervals. By leaving a page “open” after completing a memory access operation to that page, the precharge time penalty is avoided when a subsequent bank access is to that very same page (a “page hit”). However, when a subsequent bank access is to a different page (a “page miss”), the open page must then be closed and the precharge operation performed before memory access operations can proceed. Therefore, while there exist benefits to leaving a page open in the event there are frequent page hits, there exist significant time penalties associated with a large number of page misses.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for controlling data transfer operations between a memory and a device operable to rite data to and read data from the memory, in which the memory is organized as a plurality of pages. An address is stored that corresponds with an open page in the memory. A data transfer request is received, as is an address corresponding with the requested page to or from which the data transfer is to be performed. The requested page address is compared with the stored page address to determine whether the requested page is already open. If the requested page is open, data transfer operations between the device and the requested memory page are initiated. If the requested memory page is closed, the requested memory page is first opened and the data transfer operations are then initiated. If the requested data transfer is a read request, the requested memory page is left open after completion of data transfer operations. If the requested data transfer is a write request, the requested memory page is closed following completion of the data transfer operations.
REFERENCES:
patent: 5664153 (1997-09-01), Farrell
patent: 5893917 (1999-04-01), Derr
patent: 6219764 (2001-04-01), Jeddeloh
patent: 6219765 (2001-04-01), Jeddeloh
Shanley, Tom, and Don Anderson,ISA System Architecture, Addison-Wesley Publishing Company, 1995, Chap. 13, “RAM Memory: Theory of Operation,” pp. 235-272. (+ Table of Contents).
Ellis Kevin L.
Micro)n Technology, Inc.
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