Memory package method and apparatus

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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C257S202000

Reexamination Certificate

active

06222211

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to semiconductor memory devices, memory chips, memory modules, and the handling of defective memory components.
Due to the yield limitation of semiconductor fabrication process, a semiconductor memory wafer usually contains defective memory devices. These defective memory devices are declared as unusable because the defects within the device are beyond the repairing capability of the device fabrication process.
We may categorize the types of defective memory devices by the defective data bit positions. For a memory device with eight data bits, there are 255 types of defective memory devices. The large number of defective memory types further complicates the issue regarding to the handling, sorting, and packaging of these memory devices.
BRIEF SUMMARY OF THE INVENTION
This invention proposes a method and apparatus to utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a functional package.
This invention provides a method that maximizes the usage of non-defective memory data bits in the partially defective memory devices.
The present invention provides a method that reduces the complexity in the chip and module packaging, sorting, and handling.
This invention further provides a method to reduce the large number of defective memory device types.


REFERENCES:
patent: 4527251 (1985-07-01), Nibby, Jr. et al.
patent: 4774700 (1988-09-01), Satoh et al.
patent: 5128737 (1992-07-01), Van Der Have
patent: 5712816 (1998-01-01), Cappelletti et al.
patent: 5999446 (1999-12-01), Harari et al.

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