Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-01-21
2002-01-22
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000, C257S686000
Reexamination Certificate
active
06340845
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory package and more particularly to a memory package being capable of implementing two-fold memory capacity and two different memory functions on a same mounting area as would be required in a case of mounting in one stage.
2. Description of the Related Art
In recent years, it is required that a terminal of a portable device be smaller and be highly functional and there is, therefore, emerging a need for implementing more functions on smaller area of a mounting board. To achieve higher functions, it is necessary to make a memory device of large capacity and multi-functional in many cases.
FIG. 7
is a schematic circuit diagram showing a conventional memory device. For example, if the conventional memory package should be fabricated by employing a memory device
62
having a ROM (Read Only Memory) or RAM (Random Access Memory) packaged in accordance with a BGA (Ball Grid Array) packaging form, the ordinary memory device
62
is resin-molded into one package and a control circuit
61
is connected thereto.
However, since the mounting area is small in the portable device terminal or a like, there is a technological problem in that it is impossible to mount a plurality of the memory devices
62
in the same plane on the mounting area. Furthermore, there is another problem in that, when a capacity of the conventional memory device
62
becomes insufficient due to functional upgrade of the device, even if additional memory devices
62
can be further mounted in terms of mounting areas, an overall revision of the board is inevitable.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a memory package being capable of implementing two-fold memory capacity and two different memory functions on a same mounting area as would be required in a case of mounting in one stage.
According to an aspect of the present invention, there is provided a memory package for implementing two-fold memory capacity and two different memory functions on the same mounting area as would be required in the case of mounting in one stage comprising;
a plurality of memory devices each having a land formed at a predetermined position on a surface of the memory device on which another memory device is mounted and a connection pin formed at a bottom of the memory device which meets another land formed on another memory device in a one-to-one configuration at a position opposite to the land so as to be electrically connected to each other;
whereby the memory devices are stacked up and down in two stages so that the connection pins formed at the bottom of the upper memory device meet the lands formed at the predetermined position on the surface of the lower memory device on which the upper memory device is overlaid.
In the foregoing, a preferable mode is one wherein the land formed at the predetermined position on the surface of the memory device is connected, through a conductive connection pattern in a one-to-one configuration, to the connection pin formed at a position opposite to the land at the bottom of the memory device so that the land and the pin can meet each other.
Also, a preferable mode is one wherein the memory device is fabricated in accordance with a BGA packaging form.
Also, a preferable mode is one wherein each of the memory devices stacked in two stages is provided with a memory core having a same memory function and these two memory devices are so constructed that, in composite logical memory space produced by logically synthesizing one memory core being addressable by the upper memory device and the other memory core being addressable by the lower memory device, the above one memory core being addressable by the upper memory device is located at an upper part of the composite logical memory space and the other memory core being addressable by the upper memory device is located at a lower part of the composite logical memory space.
Also, a preferable mode is one wherein each of the memory devices stacked in two stages is provided with memory cores each having at least two or more memory functions and these two memory devices are so constructed that, in composite logical memory space produced by logically synthesizing one memory core being addressable by the upper memory device and the other memory core being addressable by the lower memory device, the above one memory core being addressable by the upper memory device is located at an upper part of the composite logical memory space and the other memory core being addressable by the lower memory device is located at a lower part of the composite logical memory space.
Also, a preferable mode is one that wherein comprises a control circuit used to arrange the above one memory core being addressable by the upper memory device at the upper part of the composite logical memory space and the other memory core being addressable by the lower memory device at the lower part of the composite logical memory space and to produce the composite logical memory space by logically synthesizing the above one memory core being addressable by the upper memory device and the other memory core being addressable by the lower memory device and further to perform access to the above one memory core of the upper memory device or to the other memory core of the lower memory device on the basis of the composite logical memory space.
It is also preferable that each of the memory devices stacked up and down in two stages has the memory core with a same memory function and has pins for a chip select signal and for a reserve address signal used to produce the composite logical memory space by logically synthesizing the above one memory core being addressable by the upper memory device and the other memory core being addressable by the lower memory device and wherein the above one memory core being addressable by the upper memory device is arranged at the upper part of the composite logical memory space and the other memory core being addressable by the lower memory device at the lower part of the composite logical memory space depending on a logical level provided to pins for the chip select signal and for the reserve address signal.
Also, it is preferable that each of the memory devices stacked up and down in two stages has the memory core with at least two or more memory functions and has pins for the chip select signal and for the reserve address signal used to produce the composite logical memory space by logically synthesizing the above one memory core being addressable by said upper memory device and the other memory core being addressable by the lower memory device and wherein the above one memory core being addressable by the upper memory device is arranged at the upper part of the composite logical memory space and the other memory core being addressable by the lower memory device at the lower part of the composite logical memory space depending on the logical level provided to pins for the chip select signal and for the reserve address signal.
Also, a preferable mode is one that wherein comprises the control circuit used to arrange the above one memory core being addressable by the upper memory device at the upper part of the composite logical memory space and the other memory core being addressable by the lower memory device at the lower part of the composite logical memory space depending on the logical level provided to pins for the chip select signal and for the reserve address signal and to produce the composite logical memory space by logically synthesizing the above one memory core being addressable by the upper memory device and the other memory core being addressable by the other lower memory device and further to perform access to the memory core of the upper memory device or to the memory core of the lower memory device on the basis of the composite logical memory space.
Also, a preferable mode is one wherein the memory core is provided with ROM functions.
Furthermore, a preferable mode is one wherein the memory core is
LandOfFree
Memory package implementing two-fold memory capacity and two... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory package implementing two-fold memory capacity and two..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory package implementing two-fold memory capacity and two... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2860436